Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip

2006 ◽  
Author(s):  
J.C.S. Palma ◽  
R.A.L. Reis ◽  
L. Soares Indrusiak ◽  
A. Garcia Ortiz ◽  
M. Glesner ◽  
...  
Keyword(s):  
Power Consumption ◽  
Networks On Chip ◽  
Data Encoding ◽  
On Chip ◽  
The Impact

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

Dynamically Reconfigurable Networks-on-Chip Using Runtime Adaptive Routers

2010 ◽  
pp. 28-66 ◽  
Author(s):  
Mário P. Véstias ◽  
Horácio C. Neto
Keyword(s):  
Quality Of Service ◽  
Power Consumption ◽  
First Generation ◽  
Networks On Chip ◽  
Dynamically Reconfigurable ◽  
Systems On Chip ◽  
High Bandwidth ◽  
Area Occupation ◽  
On Chip

The recent advances in IC technology have made it possible to implement systems with dozens or even hundreds of cores in a single chip. With such a large number of cores communicating with each other there is a strong pressure over the communication infrastructure to deliver high bandwidth, low latency, low power consumption and quality of service to guarantee real-time functionality. Networks-on-Chip are definitely becoming the only acceptable interconnection structure for today’s multiprocessor systems-on-chip (MPSoC). The first generation of NoC solutions considers a regular topology, typically a 2D mesh. Routers and network interfaces are mainly homogeneous so that they can be easily scaled up and modular design is facilitated. All advantages of a NoC infrastructure were proved with this first generation of NoC solutions. However, NoCs have a relative area and speed overhead. Application specific systems can benefit from heterogeneous communication infrastructures providing high bandwidth in a localized fashion where it is needed with improved area. The efficiency of both homogeneous and heterogeneous solutions can be improved if runtime changes are considered. Dynamically or runtime reconfigurable NoCs are the second generation of NoCs since they represent a new set of benefits in terms of area overhead, performance, power consumption, fault tolerance and quality of service compared to the previous generation where the architecture is decided at design time. This chapter discusses the static and runtime customization of routers and presents results with networks-on-chip with static and adaptive routers. Runtime adaptive techniques are analyzed and compared to each other in terms of area occupation and performance. The results and the discussion presented in this chapter show that dynamically adaptive routers are fundamental in the design of NoCs to satisfy the requirements of today’s systems-on-chip.

scholarly journals Coupling Routing Algorithm and Data Encoding for Low Power Networks on Chip

2015 ◽  
Vol 11 (3) ◽  
pp. 552-566 ◽  
Author(s):  
Maurizio Palesi ◽  
Davide Patti ◽  
Giuseppe Ascia ◽  
Daniela Panno ◽  
Vincenzo Catania
Keyword(s):  
Low Power ◽  
Routing Algorithm ◽  
Power Networks ◽  
Networks On Chip ◽  
Data Encoding ◽  
On Chip

Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes

2007 ◽  
Author(s):  
Jose Carlos S. Palma ◽  
Leandro S. Indrusiak ◽  
Fernando G. Moraes ◽  
Ricardo Reis ◽  
Manfred Glesner
Keyword(s):  
Power Consumption ◽  
Networks On Chip ◽  
Data Coding ◽  
Coding Schemes ◽  
On Chip

PERFORMANCE ANALYSIS OF A JPEG ENCODER MAPPED ONTO A VIRTUAL MPSoC-NoC ARCHITECTURE USING TLM 2.0.1

2013 ◽  
Vol 22 (05) ◽  
pp. 1350036
Author(s):  
F. A. ESCOBAR-JUZGA ◽  
F. E. SEGURA-QUIJANO
Keyword(s):  
Message Passing ◽  
Programming Model ◽  
Task Graph ◽  
Modeling Tools ◽  
Networks On Chip ◽  
Hardware Description ◽  
On Chip ◽  
Network Speed ◽  
High Level ◽  
The Impact

Networks on Chip (NoCs) are commonly used to integrate complex embedded systems and multiprocessor platforms due to their scalability and versatility. Modeling tools used at the functional level use SystemC to perform hardware–software co-design and error correction concurrently, thus, reducing time to market. This work analyzes a JPEG encoding algorithm mapped onto a configurable M × N, mesh/torus, NoC platform described in SystemC with the transaction level modeling (TLM) standard; timing constraints for both, the router and network interface controller, are assigned according to a hardware description language (HDL) model written for this purpose. Processing nodes are also described as SystemC threads and their computation delays are assigned depending on the amount and cost of the operations they perform. The programming model employed is message passing. We start by describing and profiling the JPEG algorithm as a task graph; then, four partitioning proposals are mapped onto three NoCs of different size. Our analysis comprises changes in topology, virtual channel depth, routing algorithms, network speed and task-node assignments. Through several high-level simulations we evaluate the impact of each parameter and we show that, for the proposed model, most improvements come from the algorithm partitioning.

Sign in / Sign up

Export Citation Format

Share Document