Low power heterogeneous 3D Networks-on-Chip architectures

2011 International Conference on High Performance Computing & Simulation ◽

10.1109/hpcsim.2011.5999871 ◽

2011 ◽

Cited By ~ 9

Author(s):

Michael Opoku Agyeman ◽

Ali Ahmadinia ◽

Alireza Shahrabi

Keyword(s):

Low Power ◽

Networks On Chip ◽

On Chip ◽

3D Networks

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A Study of Optimization Techniques for 3D Networks-on-Chip Architectures for Low Power and High Performance Applications

International Journal of Computer Applications ◽

10.5120/21541-4531 ◽

2015 ◽

Vol 121 (6) ◽

pp. 1-8 ◽

Cited By ~ 1

Author(s):

Michael OpokuAgyeman

Keyword(s):

Low Power ◽

High Performance ◽

Optimization Techniques ◽

Networks On Chip ◽

On Chip ◽

3D Networks

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The case for low-power photonic networks on chip

2007 44th ACM/IEEE Design Automation Conference ◽

10.1145/1278480.1278513 ◽

2007 ◽

Cited By ~ 39

Author(s):

Assaf Shacham ◽

Keren Bergman ◽

Luca P. Carloni

Keyword(s):

Low Power ◽

Photonic Networks ◽

Networks On Chip ◽

On Chip

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Hybrid Partially Adaptive Fault-Tolerant Routing for 3D Networks-on-Chip

Embedded Systems ◽

10.1002/9781118468654.ch10 ◽

2012 ◽

pp. 239-258

Author(s):

Sudeep Pasricha ◽

Yong Zou

Keyword(s):

Fault Tolerant ◽

Networks On Chip ◽

On Chip ◽

3D Networks

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Exploring a low-cost inter-layer communication scheme for 3D networks-on-chip

2010 15th CSI International Symposium on Computer Architecture and Digital Systems ◽

10.1109/cads.2010.5623588 ◽

2010 ◽

Cited By ~ 3

Author(s):

Amir-Mohammad Rahmani ◽

Pasi Liljeberg ◽

Juha Plosila ◽

Hannu Tenhunen

Keyword(s):

Low Cost ◽

Networks On Chip ◽

Communication Scheme ◽

On Chip ◽

3D Networks

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A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands

Integration ◽

10.1016/j.vlsi.2011.11.010 ◽

2012 ◽

Vol 45 (3) ◽

pp. 271-281 ◽

Cited By ~ 7

Author(s):

Nishit Kapadia ◽

Sudeep Pasricha

Keyword(s):

Low Power ◽

Interconnection Networks ◽

Networks On Chip ◽

On Chip ◽

Low Power Synthesis ◽

Voltage Islands

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G-CARA: A Global Congestion-Aware Routing Algorithm for traffic management in 3D networks-on-chip

2017 Iranian Conference on Electrical Engineering (ICEE) ◽

10.1109/iraniancee.2017.7985425 ◽

2017 ◽

Cited By ~ 5

Author(s):

Nooshin Nosrati ◽

Hadi Shahriar Shahhoseini

Keyword(s):

Traffic Management ◽

Routing Algorithm ◽

Networks On Chip ◽

On Chip ◽

3D Networks ◽

Congestion Aware

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An adaptive router architecture for heterogeneous 3D Networks-on-Chip

2011 NORCHIP ◽

10.1109/norchp.2011.6126725 ◽

2011 ◽

Cited By ~ 3

Author(s):

Michael Opoku Agyeman ◽

Ali Ahmadinia

Keyword(s):

Networks On Chip ◽

Router Architecture ◽

On Chip ◽

3D Networks

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3DBUFFBLESS: A novel buffered-bufferless hybrid router for 3D Networks-on-Chip

2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS) ◽

10.1109/patmos.2017.8106980 ◽

2017 ◽

Cited By ~ 3

Author(s):

K. Tatas ◽

S. Savva ◽

C. Kyriacou

Keyword(s):

Networks On Chip ◽

On Chip ◽

3D Networks

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A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip

2009 IEEE Computer Society Annual Symposium on VLSI ◽

10.1109/isvlsi.2009.19 ◽

2009 ◽

Cited By ~ 81

Author(s):

Huaxi Gu ◽

Kwai Hung Mo ◽

Jiang Xu ◽

Wei Zhang

Keyword(s):

Low Power ◽

Optical Networks ◽

Low Cost ◽

Multiprocessor Systems ◽

Optical Router ◽

Networks On Chip ◽

Systems On Chip ◽

On Chip

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Optimising Heterogeneous 3D Networks-on-Chip

2011 Sixth International Symposium on Parallel Computing in Electrical Engineering ◽

10.1109/parelec.2011.40 ◽

2011 ◽

Cited By ~ 4

Author(s):

Michael Opoku Agyeman ◽

Ali Ahmadinia

Keyword(s):

Networks On Chip ◽

On Chip ◽

3D Networks

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