Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool

2008 ◽  
Author(s):  
Morteza Damavandpeyma ◽  
Siamak Mohammadi
Keyword(s):  
Data Flow ◽  
Control Data ◽  
Architectural Synthesis ◽  
Cad Tool

scholarly journals System-level Time-stationary Control Synthesis for Pipelined Data Paths

VLSI Design ◽  
1999 ◽  
Vol 9 (2) ◽  
pp. 159-180
Author(s):  
Jong Tae Kim ◽  
Fadi J. Kurdahi ◽  
Noh Byung Park
Keyword(s):  
Data Flow ◽  
System Level ◽  
Control Synthesis ◽  
State Transitions ◽  
Data Flow Graph ◽  
Control Data ◽  
Flow Graph ◽  
High Level ◽  
Horizontal Partitioning ◽  
Stationary Control

We address the prblem of time-stationary control synthesis for pipelined data paths. Control synthesis system accepts scheduled control data flow graph with conditional branches which are produced by high level synthesis tools such as Sehwa [1] as input specification and generates a FSM controller. First a scheduled control/data flow graph is analyzed and the various states are identified. Overlapped states are grouped together to produce L groups where L is the pipeline latency. Next, state transitions are identified and a state table is generated. Finally, a highly optimized FSM controller is implemented by performing horizontal partitioning and the corresponding stae encoding so as to minimize the total controller area. We compared our approach to published work on FSM generation and optimization and the results indicate that our method results in large savings in total controller area.

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