Low-leakage WSe2 FET gate-stack using titanyl phthalocyanine seeding layer for atomic layer deposition of Al2O3

2015 ◽  
Author(s):  
Sara Fathipour ◽  
Jun Hong Park ◽  
Andrew Kummel ◽  
Alan Seabaugh
Keyword(s):  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Gate Stack ◽  
Seeding Layer ◽  
Low Leakage ◽  
Layer Deposition ◽  
Titanyl Phthalocyanine

scholarly journals Atomic Layer Deposition (ALD) of Metal Gates for CMOS

2019 ◽  
Vol 9 (11) ◽  
pp. 2388 ◽  
Author(s):  
Chao Zhao ◽  
Jinjuan Xiang
Keyword(s):  
Atomic Layer Deposition ◽  
Field Effect Transistors ◽  
Material Selection ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Metal Gate ◽  
Gate Stack ◽  
Short Channel ◽  
Metal Gates ◽  
Layer Deposition

The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.

Low Dit HfO2/Al2O3/In0.53Ga0.47As gate stack achieved with plasma-enhanced atomic layer deposition

2015 ◽  
Vol 147 ◽  
pp. 231-234 ◽  
Author(s):  
Vladimir Djara ◽  
Marilyne Sousa ◽  
Nikola Dordevic ◽  
Lukas Czornomaz ◽  
Veeresh Deshpande ◽  
...  
Keyword(s):  
Atomic Layer Deposition ◽  
Atomic Layer ◽  
Gate Stack ◽  
Layer Deposition

scholarly journals Electrostatic Supercapacitors by Atomic Layer Deposition on Nanoporous Anodic Alumina Templates for Environmentally Sustainable Energy Storage

Coatings ◽  
2018 ◽  
Vol 8 (11) ◽  
pp. 403 ◽  
Author(s):  
Luis Fernández-Menéndez ◽  
Ana González ◽  
Víctor Vega ◽  
Víctor de la Prida
Keyword(s):  
Atomic Layer Deposition ◽  
Silicon Dioxide ◽  
Atomic Layer ◽  
Dielectric Materials ◽  
Anodic Alumina ◽  
Layer By Layer ◽  
Nanoporous Anodic Alumina ◽  
Low Leakage ◽  
Layer Deposition ◽  
Anodic Alumina Templates

In this work, the entire manufacturing process of electrostatic supercapacitors using the atomic layer deposition (ALD) technique combined with the employment of nanoporous anodic alumina templates as starting substrates is reported. The structure of a usual electrostatic capacitor, which comprises a top conductor electrode/the insulating dielectric layer/and bottom conductor electrode (C/D/C), has been reduced to nanoscale size by depositing layer by layer the required materials over patterned nanoporous anodic alumina membranes (NAAMs) by employing the ALD technique. A thin layer of aluminum-doped zinc oxide, with 3 nm in thickness, is used as both the top and bottom electrodes’ material. Two dielectric materials were tested; on the one hand, a triple-layer made by a successive combination of 3 nm each layers of silicon dioxide/titanium dioxide/silicon dioxide and on the other hand, a simple layer of alumina, both with 9 nm in total thickness. The electrical properties of these capacitors are studied, such as the impedance and capacitance dependences on the AC frequency regime (up to 10 MHz) or capacitance (180 nF/cm2) on the DC regime. High breakdown voltage values of 60 V along with low leakage currents (0.4 μA/cm2) are also measured from DC charge/discharge RC circuits to determine the main features of the capacitors behavior integrated in a real circuit.

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