Modulating the Interface Quality and Electrical Properties of HfTiO/InGaAs Gate Stack by Atomic-Layer-Deposition-Derived Al2O3Passivation Layer

2014 ◽  
Vol 6 (24) ◽  
pp. 22013-22025 ◽  
Author(s):  
Gang He ◽  
Juan Gao ◽  
Hanshuang Chen ◽  
Jingbiao Cui ◽  
Zhaoqi Sun ◽  
...  
2016 ◽  
Vol 55 (8S2) ◽  
pp. 08PC05 ◽  
Author(s):  
Masayuki Kanematsu ◽  
Shigehisa Shibayama ◽  
Mitsuo Sakashita ◽  
Wakana Takeuchi ◽  
Osamu Nakatsuka ◽  
...  

Coatings ◽  
2020 ◽  
Vol 10 (7) ◽  
pp. 692
Author(s):  
Jong Hyeon Won ◽  
Seong Ho Han ◽  
Bo Keun Park ◽  
Taek-Mo Chung ◽  
Jeong Hwan Han

Herein, we performed a comparative study of plasma-enhanced atomic layer deposition (PEALD) of SnO2 films using Sn(dmamp)2 as the Sn source and either H2O plasma or O2 plasma as the oxygen source in a wide temperature range of 100–300 °C. Since the type of oxygen source employed in PEALD determines the growth behavior and resultant film properties, we investigated the growth feature of both SnO2 PEALD processes and the various chemical, structural, morphological, optical, and electrical properties of SnO2 films, depending on the oxygen source. SnO2 films from Sn(dmamp)2/H2O plasma (SH-SnO2) and Sn(dmamp)2/O2 plasma (SO-SnO2) showed self-limiting atomic layer deposition (ALD) growth behavior with growth rates of ~0.21 and 0.07–0.13 nm/cycle, respectively. SO-SnO2 films showed relatively larger grain structures than SH-SnO2 films at all temperatures. Interestingly, SH-SnO2 films grown at high temperatures of 250 and 300 °C presented porous rod-shaped surface morphology. SO-SnO2 films showed good electrical properties, such as high mobility up to 27 cm2 V−1·s−1 and high carrier concentration of ~1019 cm−3, whereas SH-SnO2 films exhibited poor Hall mobility of 0.3–1.4 cm2 V−1·s−1 and moderate carrier concentration of 1 × 1017–30 × 1017 cm−3. This may be attributed to the significant grain boundary and hydrogen impurity scattering.


2019 ◽  
Vol 9 (11) ◽  
pp. 2388 ◽  
Author(s):  
Chao Zhao ◽  
Jinjuan Xiang

The continuous down-scaling of complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) had been suffering two fateful technical issues, one relative to the thinning of gate dielectric and the other to the aggressive shortening of channel in last 20 years. To solve the first issue, the high-κ dielectric and metal gate technology had been induced to replace the conventional gate stack of silicon dioxide layer and poly-silicon. To suppress the short channel effects, device architecture had changed from planar bulk Si device to fully depleted silicon on insulator (FDSOI) and FinFETs, and will transit to gate all-around FETs (GAA-FETs). Different from the planar devices, the FinFETs and GAA-FETs have a 3D channel. The conventional high-κ/metal gate process using sputtering faces conformality difficulty, and all atomic layer deposition (ALD) of gate stack become necessary. This review covers both scientific and technological parts related to the ALD of metal gates including the concept of effect work function, the material selection, the precursors for the deposition, the threshold voltage (Vt) tuning of the metal gate in contact with HfO2/SiO2/Si. The ALD of n-type metal gate will be detailed systematically, based mainly on the authors’ works in last five years, and the all ALD gate stacks will be proposed for the future generations based on the learning.


2005 ◽  
Vol 86 (22) ◽  
pp. 222904 ◽  
Author(s):  
Satoshi Kamiyama ◽  
Takayoshi Miura ◽  
Yasuo Nara ◽  
Tsunetoshi Arikado

2017 ◽  
Vol 7 (1) ◽  
Author(s):  
Min Baik ◽  
Hang-Kyu Kang ◽  
Yu-Seon Kang ◽  
Kwang-Sik Jeong ◽  
Youngseo An ◽  
...  

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