Direct evidence for multiple vibrational excitation of Si-H/D bonds for hot-carrier degradation of MOS transistors

2003 ◽  
Author(s):  
Zhi Chen ◽  
Pangleen Ong
Keyword(s):  
Direct Evidence ◽  
Vibrational Excitation ◽  
Mos Transistors ◽  
Hot Carrier ◽  
Hot Carrier Degradation

ANALYSIS OF HOT CARRIER DEGRADATION IN AC STRESSED N-CHANNEL MOS TRANSISTORS USING THE CHARGE PUMPING TECHNIQUE

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-651-C4-655 ◽  
Author(s):  
R. BELLENS ◽  
P. HEREMANS ◽  
G. GROESENEKEN ◽  
H. E. MAES
Keyword(s):  
Mos Transistors ◽  
Charge Pumping ◽  
Hot Carrier ◽  
Hot Carrier Degradation

Deuterium isotope effect for AC and DC hot-carrier degradation of MOS transistors: a comparison study

2001 ◽  
Vol 48 (4) ◽  
pp. 813-815
Author(s):  
Zhi Chen ◽  
Kangguo Cheng ◽  
Jinju Lee ◽  
J.W. Lyding ◽  
K. Hess ◽  
...  
Keyword(s):  
Isotope Effect ◽  
Comparison Study ◽  
Mos Transistors ◽  
Deuterium Isotope Effect ◽  
Hot Carrier ◽  
Hot Carrier Degradation

Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors

2002 ◽  
Vol 716 ◽  
Author(s):  
Nihar Ranjan Mohapatra ◽  
Souvik Mahapatra ◽  
V. Ramgopal Rao
Keyword(s):  
Flash Memory ◽  
Degradation Mechanism ◽  
Carrier Injection ◽  
Scaling Effects ◽  
Mos Transistors ◽  
Gate Current ◽  
Hot Carrier ◽  
Wide Range ◽  
Injection Mechanism ◽  
Hot Carrier Degradation

AbstractThis paper analyzes in detail the substrate enhanced gate current injection mechanism and the resulting hot-carrier degradation in n-channel MOS transistors and compares the results with conventional channel hot carrier injection mechanism. The degradation mechanism is studied for different values of substrate voltage over a wide range of channel length and oxide thickness. Stress and charge pumping measurements are carried out to study the degradation under identical bias (gate, drain, substrate) and gate current condition. The influence of device dimensions on the gate injection efficiency and hot carrier degradation is also studied. Results show that the degradation under negative substrate voltage operation is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanism responsible for such trends is discussed. It is also found that, under identical gate current (programming time in flash memory cells), the degradation is less for higher negative substrate bias, which is helpful in realizing fast and reliable flash memories.

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