A Prevenient Voltage Stress Test Method for High Density Memory

2008 ◽  
Author(s):  
Jongsoo Yim ◽  
Gunbae Kim ◽  
Incheol Nam ◽  
Sangki Son ◽  
Jonghyoung Lim ◽  
...  
Keyword(s):  
Stress Test ◽  
High Density ◽  
Test Method ◽  
Voltage Stress

scholarly journals Development of Tensile Test Method for High-density Coal under Carbonization

1998 ◽  
Vol 84 (5) ◽  
pp. 321-326 ◽  
Author(s):  
Akira SUZUKI ◽  
Makoto UEKI ◽  
Hideyuki AOKI ◽  
Takatoshi MIURA ◽  
Kenji KATO ◽  
...  
Keyword(s):  
Tensile Test ◽  
High Density ◽  
Test Method

Research on Gear Contact Fatigue Stress Test

2011 ◽  
Vol 86 ◽  
pp. 825-828
Author(s):  
Tie Wang ◽  
Hong Mei Li ◽  
Rui Liang Zhang ◽  
Zhi Fei Wu
Keyword(s):  
Damage Accumulation ◽  
Stress Test ◽  
Contact Fatigue ◽  
Test Method ◽  
Fatigue Stress ◽  
Accumulation Curve ◽  
Limit Value ◽  
Fatigue Damage Accumulation ◽  
Gear Contact ◽  
The Cost

This paper put forward the rapid measure method of the gear contact fatigue stress value with a few gear samples, which can get the estimated value of the gear fatigue limit value precisely and rapidly. And the gear fatigue life curve and fatigue damage accumulation curve are simulated by MATLAB. Comparing with the traditional test method, this method can reduce the cost and save the time.

Precise Chip Joint Method with Sub-micron Au Particle for High-density SiC Power Module Operating at High Temperature

2013 ◽  
Vol 2013 (HITEN) ◽  
pp. 000254-000259 ◽  
Author(s):  
Fumiki Kato ◽  
Fengqun Lang ◽  
Simanjorang Rejeki ◽  
Hiroshi Nakagawa ◽  
Hiroshi Yamaguchi ◽  
...  
Keyword(s):  
Shear Strength ◽  
High Temperature ◽  
Flip Chip ◽  
Stress Test ◽  
High Density ◽  
Cathode Side ◽  
Module Structure ◽  
Power Devices ◽  
Power Module ◽  
Joint Method

In this work, a novel precise chip joint method using sub-micron Au particle for high-density silicon carbide (SiC) power module operating at high temperature is proposed. A module structure of SiC power devices are sandwiched between two silicon nitride-active metal brazed copper (SiN-AMC) circuit boards. To make a precise position and height control of the chip bonding, the top side (gate/source or anode pad side) of SiC power devices are flip-chip bonded to circuit electrodes using sub-micron Au particle with low temperature (250°C) and pressure-less sintering. The accuracy of the bonding position of chips was less than 10 μm and the accuracy of the height after bonding chips was less than 15 μm. Mechanical shear fatigue tests for flip-chip bonded SiC Schottky barrier diode (SBD) were carried out. As a result, initial shear strength of the joint was 36 MPa. The shear strength of 43 MPa is obtained after storage life test (500 hours at 250°C), and also 35 MPa is obtained even after thermal cycle stress test (1000 cycles between −40°C and 250°C). The flip-chip bonding of SiC-JFET is successfully realizedon the substrate without short or open failure electrically. Finally we joint the backside of the SiC-JFET (drain side) and the SiC-SBD (cathode side) to each circuit electrodes at once by means of reflow process with Au-12%Ge solder. The structured sandwich SiC power module was also successfully formed.

Reducing burn-in time through high-voltage stress test and Weibull statistical analysis

2006 ◽  
Vol 23 (2) ◽  
pp. 88-98 ◽  
Author(s):  
M.F. Zakaria ◽  
Z.A. Kassim ◽  
M.P.-L. Ooi ◽  
S. Demidenko
Keyword(s):  
Statistical Analysis ◽  
High Voltage ◽  
Stress Test ◽  
Weibull Statistical Analysis ◽  
Voltage Stress
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