Modifying test vectors for reducing power dissipation in CMOS circuits

2003 ◽  
Author(s):  
Y. Higami ◽  
S. Kobayashi ◽  
Y. Takamatsu
Keyword(s):  
Power Dissipation ◽  
Reducing Power ◽  
Cmos Circuits ◽  
Test Vectors

Power-Delay Trade-Offs in Complementary Metal-Oxide Semiconductor Circuits Using Self and Optimum Bulk Control

2020 ◽  
Vol 18 (3) ◽  
pp. 210-215
Author(s):  
Shubham Tayal ◽  
Sunil Jadav
Keyword(s):  
Power Dissipation ◽  
Complementary Metal Oxide Semiconductor ◽  
Joint Effect ◽  
Sequential Circuits ◽  
Vlsi Circuits ◽  
Oxide Semiconductor ◽  
Cmos Circuits ◽  
Trade Offs ◽  
Self Bias ◽  
Semiconductor Circuits

Power dissipation and delay are the challenging issues in the design of VLSI circuits. This manuscript explores joint effect of Self-Bias transistors (SBTs) and Optimum Bulk Bias Technique (OBBT) on CMOS circuits. Earlier investigations on SBTs shows decrease in power dissipation of combinational as well as sequential circuits. We extend the analysis by studying the effect of OBBT on the static and dynamic power of CMOS circuits with SBTs coupled amid the pull-up/down network and the supply bars. Extensive SPICE simulations have been carried out in 0.18 μm technology. Results demonstrate that, a 73% drop in power in case of combinational circuits and 43% in case of sequential circuits can be accomplished by engaging OBBT in digital circuits. Trade-off between power and delay is also been presented.

Bus-switch coding for reducing power dissipation in off-chip buses

2004 ◽  
Vol 12 (12) ◽  
pp. 1374-1377 ◽  
Author(s):  
M. Olivieri ◽  
F. Pappalardo ◽  
G. Visalli
Keyword(s):  
Power Dissipation ◽  
Reducing Power

scholarly journals Estimation of Leakage Power and Delay in CMOS Circuits

2020 ◽  
Vol 4 (7) ◽  
pp. 14-19
Author(s):  
Mohasinul Huq N Md ◽  
Mohan Das S ◽  
Bilal N Md
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Full Adder ◽  
Cmos Technology ◽  
Propagation Delay ◽  
Leakage Power ◽  
Nand Gate ◽  
High Threshold ◽  
Cmos Circuits ◽  
Low Leakage

This paper presents an estimation of leakage power and delay for 1-bit Full Adder (FA)designed which is based on Leakage Control Transistor (LCT) NAND gates as basic building block. The main objective is to design low leakage full adder circuit with the help of low and high threshold transistors. The simulations for the designed circuits performed in cadence virtuoso tool with 45 nm CMOS technology at a supply voltage of 0.9 Volts. Further, analysis of effect of parametric variation on leakage current and propagation delay in CMOS circuits is performed. The saving in leakage power dissipation for LCT NAND_HVT gate is up to 72.33% and 45.64% when compared to basic NAND and LCT NAND gate. Similarly for 1-bit full adder the saving is up to 90.9% and 40.08% when compared to basic NAND FA and LCT NAND.

scholarly journals Ring Counter Based ATPG for Low Transition Test Pattern Generation

2015 ◽  
Vol 2015 ◽  
pp. 1-6
Author(s):  
V. M. Thoulath Begam ◽  
S. Baulkani
Keyword(s):  
Power Dissipation ◽  
Peak Power ◽  
Test Pattern ◽  
Average Power ◽  
Pattern Generation ◽  
External Circuit ◽  
Dynamic Power ◽  
Ring Counter ◽  
Random Fashion ◽  
Test Vectors

In test mode test patterns are applied in random fashion to the circuit under circuit. This increases switching transition between the consecutive test patterns and thereby increases dynamic power dissipation. The proposed ring counter based ATPG reduces vertical switching transitions by inserting test vectors only between the less correlative test patterns. This paper presents the RC-ATPG with an external circuit. The external circuit consists of XOR gates, full adders, and multiplexers. First the total number of transitions between the consecutive test patterns is determined. If it is more, then the external circuit generates and inserts test vectors in between the two test patterns. Test vector insertion increases the correlation between the test patterns and reduces dynamic power dissipation. The results prove that the test patterns generated by the proposed ATPG have fewer transitions than the conventional ATPG. Experimental results based on ISCAS’85 and ISCAS’89 benchmark circuits show 38.5% reduction in the average power and 50% reduction in the peak power attained during testing with a small size decoding logic.

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