LFSR Reseeding Based Test Compression Respecting Different Controllability of Decompressor Outputs

2015 ◽  
Author(s):  
Ondrej Novak ◽  
Jiri Jenicek ◽  
Martin Rozkovec
Keyword(s):  
Test Compression ◽  
Lfsr Reseeding

LFSR Reseeding-Oriented Low-Power Test-Compression Architecture for Scan Designs

2018 ◽  
Vol 34 (6) ◽  
pp. 685-695 ◽  
Author(s):  
Haiying Yuan ◽  
Changshi Zhou ◽  
Xun Sun ◽  
Kai Zhang ◽  
Tong Zheng ◽  
...  
Keyword(s):  
Low Power ◽  
Power Test ◽  
Test Compression ◽  
Low Power Test ◽  
Lfsr Reseeding

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

LFSR reseeding method based on dividing test cubes by equal number of specified bits

2009 ◽  
Vol 2009 (10) ◽  
pp. 55-61
Author(s):  
Huaguo Liang ◽  
Wangyan Cheng ◽  
Yang Li ◽  
Wei Mao
Keyword(s):  
Lfsr Reseeding
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