Fault-tolerant 2-D Mesh Network-On-Chip for MultiProcessor Systems-on-Chip

2006 ◽  
Author(s):  
H. Kariniemi ◽  
J. Nurmi
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Mesh Network ◽  
Multiprocessor Systems ◽  
Systems On Chip ◽  
On Chip

A Fault-Tolerant Routing Algorithm Using Tunnels in Fault Blocks for Network-on-Chip

2017 ◽  
Vol 27 (02) ◽  
pp. 1850022 ◽  
Author(s):  
Ling Wang ◽  
Terrence Mak
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithm ◽  
Network On Chip ◽  
Mesh Network ◽  
Communication Performance ◽  
Simulation Results ◽  
On Chip

In 2D mesh Network on Chips (NoCs), fault-tolerant algorithms usually deactivate healthy nodes to form rectangular or convex fault blocks. However, the deactivated nodes can possibly form an available tunnel in a faulty block. We propose a method to discover these tunnels, and propose a fault-tolerant routing algorithm to route messages through such paths such that the overall communication performance is improved. In addition, the algorithm is deadlock-free by prohibiting some turns. Simulation results demonstrate that the reuse of the sacrificed nodes in fault blocks can significantly reduce the average message latency.

Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip

2019 ◽  
pp. 495-506 ◽  
Author(s):  
Akshay B. P. ◽  
Ganesh K. M. ◽  
Thippeswamy D. R. ◽  
Vishnu S. Bhat ◽  
Anitha Vijayakumar ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Mesh Network ◽  
On Chip

A Region-based Fault-Tolerant Routing Algorithmfor 2D Irregular Mesh Network-on-Chip

2013 ◽  
Vol 29 (3) ◽  
pp. 415-429 ◽  
Author(s):  
Yusuke Fukushima ◽  
Masaru Fukushi ◽  
Ikuko Eguchi Yairi
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Mesh Network ◽  
Irregular Mesh ◽  
On Chip

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

2012 ◽  
pp. 263-277
Author(s):  
Sanna Määttä ◽  
Leandro Möller ◽  
Leandro Soares Indrusiak ◽  
Luciano Ost ◽  
Manfred Glesner ◽  
...  
Keyword(s):  
Design Space Exploration ◽  
Space Exploration ◽  
Network On Chip ◽  
Multiprocessor Systems ◽  
Trade Off ◽  
Successive Refinement ◽  
Systems On Chip ◽  
On Chip ◽  
Abstraction Levels

Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.

Architecture and Network-on-Chip Implementation of a New Hierarchical Interconnection Network

2014 ◽  
Vol 24 (02) ◽  
pp. 1540006 ◽  
Author(s):  
M. M. Hafizur Rahman ◽  
Rizal Mohd Nor ◽  
Tengku Mohd Bin Tengku Sembok ◽  
M. A. H. Akhand
Keyword(s):  
Mesh Networks ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Average Distance ◽  
Small Diameter ◽  
Network On Chip ◽  
Mesh Network ◽  
Minimal Distance ◽  
Bisection Width ◽  
On Chip

A Midimew-connected Mesh Network (MMN) is a minimal distance mesh with wrap-around links network of multiple basic modules (BMs), in which the BMs are 2D-mesh networks that are hierarchically interconnected for higher-level networks. In this paper, we present the architecture of the MMN, addressing of node, routing of message, and evaluate the static network performance of MMN, TESH, mesh and torus networks. In addition, we propose the network-on-chip (NoC) implementation of MMN. With innovative combination of diagonal and hierarchical structure, the MMN possesses several attractive features, including constant degree, small diameter, low cost, small average distance, moderate bisection width and high fault tolerant performance than that of other conventional and hierarchical interconnection networks. The simple architecture of MMN is also highly suitable for NoC implementation. To implement all the links of level-3 MMN, only four layers are needed which is feasible with current and future VLSI technologies.

TRACK: An algorithm for fault-tolerant, dynamic and scalable 2D mesh network-on-chip routing reconfiguration

Integration ◽  
2020 ◽  
Vol 72 ◽  
pp. 92-110
Author(s):  
Anugrah Jain ◽  
Vijay Laxmi ◽  
Meenakshi Tripathi ◽  
Manoj Singh Gaur ◽  
Rimpy Bishnoi
Keyword(s):  
Fault Tolerant ◽  
Network On Chip ◽  
Mesh Network ◽  
On Chip
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