Low power pipelined successive approximation A/D converter

2002 ◽  
Author(s):  
Shouli Yan ◽  
F. Maloberti ◽  
Jinghua Li
Keyword(s):  
Low Power ◽  
Successive Approximation

Low Power Design of a 1 V 8-bit 125 fJ Asynchronous SAR ADC with Binary Weighted Capacitive DAC

2017 ◽  
Vol 26 (05) ◽  
pp. 1750077 ◽  
Author(s):  
Anush Bekal ◽  
Shabi Tabassum ◽  
Manish Goswami
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Digital Control ◽  
Low Power Design ◽  
Cmos Technology ◽  
Control Logic ◽  
Control Block ◽  
Logic Block ◽  
External Clock ◽  
Asynchronous Sar

The work proposes an improved technique to design a low power 8-bit asynchronous successive approximation register (ASAR), an analog-to-digital converter (ADC). The proposed ASAR ADC consists of a comparator, ASAR (digital control logic block), and a capacitive-digital-to-analog convertor (C-DAC). The comparator is a preamplier-based improved positive feedback latch circuit which has a built-in sample and hold (S/H) functionality and saves an enormous amount of power. The implemented digital control logic block performing the successive approximation (SA) algorithm is totally unrestrained of the external clock pulse. The outputs from the comparator are given to a XOR logic whose outputs serve as an internally generated clock (ready signal) to trigger the digital control block. Hence, an external clock is not required to initiate the digital control block making its operation asynchronous. By implementing this, the ADC can circumvent the usage of an oversampled clock and can operate on a single low-speed sample clock. This, in turn, saves power and it cuts down the required resilience in sampling rates. The proposed ADC has been designed and simulated using UMC-0.18[Formula: see text][Formula: see text]m CMOS technology which dissipates 32.18[Formula: see text][Formula: see text]W power when operated on a single 1[Formula: see text]V power supply and achieves complete 8-bit conversion in 1.09[Formula: see text][Formula: see text]s. The relative accuracy of capacitor ratio, aperture jitter and FOM are 0.39[Formula: see text], 1.2[Formula: see text]ns and 125[Formula: see text]fJ/conversion-step, respectively.

A new successive approximation architecture for high-speed low-power ADCs

2006 ◽  
Vol 60 (3) ◽  
pp. 217-223 ◽  
Author(s):  
Khosrov Dabbagh-Sadeghipour ◽  
Khayrollah Hadidi ◽  
Abdollah Khoei
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
High Speed

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450023
Author(s):  
MOHAMED O. SHAKER ◽  
MAGDY A. BAYOUMI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Power Supply ◽  
Cmos Technology ◽  
Clock Signal ◽  
Switching Activity ◽  
Successive Approximation Register ◽  
Simulation Results ◽  
Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

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