Low Power Illinois Scan Architecture for Simultaneous Power and Test Data Volume Reduction

2008 Design, Automation and Test in Europe ◽

10.1109/date.2008.4484724 ◽

2008 ◽

Cited By ~ 8

Author(s):

Anshuman Chandra ◽

Felix Ng ◽

Rohit Kapur

Keyword(s):

Low Power ◽

Test Data ◽

Volume Reduction ◽

Data Volume

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Low power Illinois scan architecture for simultaneous power and test data volume reduction

2008 Design, Automation and Test in Europe ◽

10.1145/1403375.1403486 ◽

2008 ◽

Cited By ~ 11

Author(s):

Anshuman Chandra ◽

Felix Ng ◽

Rohit Kapur

Keyword(s):

Low Power ◽

Test Data ◽

Volume Reduction ◽

Data Volume

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Scan test data volume reduction in multi-clocked designs with safe capture technique

Proceedings. International Test Conference ◽

10.1109/test.2002.1041755 ◽

2003 ◽

Cited By ~ 22

Author(s):

V. Jain ◽

J. Waicukauski

Keyword(s):

Test Data ◽

Volume Reduction ◽

Scan Test ◽

Data Volume ◽

Capture Technique

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Input Test Data Volume Reduction Using Seed Complementation and Multiple LFSRs

2020 IEEE 38th VLSI Test Symposium (VTS) ◽

10.1109/vts48691.2020.9107617 ◽

2020 ◽

Author(s):

Irith Pomeranz

Keyword(s):

Test Data ◽

Volume Reduction ◽

Data Volume ◽

Input Test

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A Unified Approach to Test Generation and Test Data Volume Reduction

2006 IEEE International Test Conference ◽

10.1109/test.2006.297644 ◽

2006 ◽

Cited By ~ 3

Author(s):

Yung-chieh Lin ◽

Kwang-ting Cheng

Keyword(s):

Test Data ◽

Test Generation ◽

Volume Reduction ◽

Unified Approach ◽

Data Volume

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Low Power Test-Compression for High Test-Quality and Low Test-Data Volume

2011 Asian Test Symposium ◽

10.1109/ats.2011.75 ◽

2011 ◽

Cited By ~ 6

Author(s):

Vasileios Tenentes ◽

Xrysovalantis Kavousianos

Keyword(s):

Low Power ◽

Test Data ◽

Test Quality ◽

Power Test ◽

Test Compression ◽

Low Power Test ◽

Data Volume ◽

High Test

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Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating

2011 Asian Test Symposium ◽

10.1109/ats.2011.46 ◽

2011 ◽

Cited By ~ 6

Author(s):

Elham K. Moghaddam ◽

Janusz Rajski ◽

Sudhakar M. Reddy ◽

Jakub Janicki

Keyword(s):

Low Power ◽

Test Data ◽

Clock Gating ◽

Data Volume ◽

Delay Tests

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Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing

2008 Design, Automation and Test in Europe ◽

10.1109/date.2008.4484683 ◽

2008 ◽

Cited By ~ 3

Author(s):

Ozgur Sinanoglu ◽

Erik Jan Marinissen

Keyword(s):

Test Data ◽

Volume Reduction ◽

Soc Testing ◽

Data Volume

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Multimode Illinois Scan Architecture for Test Application Time and Test Data Volume Reduction

25th IEEE VLSI Test Symmposium (VTS'07) ◽

10.1109/vts.2007.39 ◽

2007 ◽

Cited By ~ 18

Author(s):

Anshuman Chandra ◽

Haihua Yan ◽

Rohit Kapur

Keyword(s):

Test Data ◽

Volume Reduction ◽

Application Time ◽

Test Application Time ◽

Test Application ◽

Data Volume

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Combined input test data volume reduction for mixed broadside and skewed‐load test sets

IET Computers & Digital Techniques ◽

10.1049/iet-cdt.2015.0117 ◽

2016 ◽

Vol 10 (3) ◽

pp. 138-145

Author(s):

Irith Pomeranz

Keyword(s):

Test Data ◽

Load Test ◽

Volume Reduction ◽

Data Volume ◽

Test Sets ◽

Input Test

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Analysis of the test data volume reduction benefit of modular SOC testing

2008 Design, Automation and Test in Europe ◽

10.1145/1403375.1403421 ◽

2008 ◽

Cited By ~ 1

Author(s):

Ozgur Sinanoglu ◽

Erik Jan Marinissen

Keyword(s):

Test Data ◽

Volume Reduction ◽

Soc Testing ◽

Data Volume

Download Full-text