scholarly journals Optimized Integration of Test Compression and Sharing for SOC Testing

2007 ◽  
Author(s):  
Anders Larsson ◽  
Erik Larsson ◽  
Petru Eles ◽  
Zebo Peng
Keyword(s):  
Test Compression ◽  
Soc Testing

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

scholarly journals Defect Coverage-Driven Window-Based Test Compression

2010 ◽  
Author(s):  
Xrysovalantis Kavousianos ◽  
Krishnendu Chakrabarty ◽  
Emmanouil Kalligeros ◽  
Vasileios Tenentes
Keyword(s):  
Defect Coverage ◽  
Test Compression

Design of Test Compression for Multiple Scan Chains Circuits

2021 ◽  
Author(s):  
D Manasa Manikya ◽  
Marala Jagruthi ◽  
Rana Anjum ◽  
Ashok Kumar K
Keyword(s):  
Test Compression ◽  
Multiple Scan ◽  
Scan Chains

On using implied values in EDT-based test compression

2014 ◽  
Author(s):  
Marcin Gebala ◽  
Grzegorz Mrugalski ◽  
Nilanjan Mukherjee ◽  
Janusz Rajski ◽  
Jerzy Tyszer
Keyword(s):  
Test Compression
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