Performance Evaluation for System-on-Chip Architectures using Trace-based Transaction Level Simulation

2006 ◽  
Author(s):  
T. Wild ◽  
A. Herkersdorf ◽  
R. Ohlendorf
Keyword(s):  
Performance Evaluation ◽  
System On Chip ◽  
Transaction Level ◽  
On Chip

scholarly journals SystemC Transaction-Level Modeling of an MPSoC Platform Based on an Open Source ISS by Using Interprocess Communication

2008 ◽  
Vol 2008 ◽  
pp. 1-10
Author(s):  
Sami Boukhechem ◽  
El-Bay Bourennane
Keyword(s):  
Open Source ◽  
System On Chip ◽  
Open Architecture ◽  
Multiprocessor System ◽  
Instruction Set ◽  
Levels Of Abstraction ◽  
Transaction Level Modeling ◽  
Synthesis Tool ◽  
Transaction Level ◽  
On Chip

Transaction-level modeling (TLM) is a promising technique to deal with the increasing complexity of modern embedded systems. This model allows a system designer to model a complete application, composed of hardware and software parts, at several levels of abstraction. For this purpose, we use systemC, which is proposed as a standardized modeling language. This paper presents a transaction-level modeling cosimulation methodology for modeling, validating, and verifying our embedded open architecture platform. The proposed platform is an open source multiprocessor system-on-chip (MPSoC) platform, integrated under the synthesis tool for adaptive and reconfigurable system-on-chip (STARSoC) environment. It relies on the integration between an open source instruction set simulators (ISSs), OR1Ksim platform, and the systemC simulation environment which contains other components (wishbone bus, memories, , etc.). The aim of this work is to provide designers with the possibility of faster and efficient architecture exploration at a higher level of abstractions, starting from an algorithmic description to implementation details.

WiFi HaLow for Long-Range and Low-Power Internet of Things: System on Chip Development and Performance Evaluation

2021 ◽  
Vol 59 (7) ◽  
pp. 101-107
Author(s):  
Il-Gu Lee ◽  
Duk Bai Kim ◽  
Jeongki Choi ◽  
Hyungu Park ◽  
Sok-Kyu Lee ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Internet Of Things ◽  
Low Power ◽  
Long Range ◽  
System On Chip ◽  
And Performance ◽  
On Chip

Design and performance evaluation of on chip network with Transaction Level Modeling

2011 ◽  
Author(s):  
Nourddine Abid ◽  
Wissem Chouchene ◽  
Brahim Attia ◽  
Abdelrim Zitouni ◽  
Rached Tourki
Keyword(s):  
Performance Evaluation ◽  
Transaction Level Modeling ◽  
Transaction Level ◽  
And Performance ◽  
On Chip
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