Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004.
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Approaching interoperability from the bottom up:a lattice structure for the object-oriented method for interoperability (OOMI)

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004. ◽

10.1109/iwrsp.2004.1311108 ◽

2004 ◽

Author(s):

G.M. Lawler ◽

P.E. Young

Keyword(s):

Lattice Structure ◽

Object Oriented ◽

Object Oriented Method

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Automated hardware synthesis from formal specification using sat solvers

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004. ◽

10.1109/iwrsp.2004.1311089 ◽

2004 ◽

Cited By ~ 1

Author(s):

D. Greaves

Keyword(s):

Formal Specification ◽

Hardware Synthesis ◽

Sat Solvers

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Network interface generation for mpsoc: from communication service requirements to rtl implementation

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004. ◽

10.1109/iwrsp.2004.1311097 ◽

2004 ◽

Cited By ~ 3

Author(s):

A. Grasset ◽

F. Rousseau ◽

A.A. Jerraya

Keyword(s):

Network Interface ◽

Communication Service ◽

Interface Generation

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Towards formal verification on the system level

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004. ◽

10.1109/iwrsp.2004.1311087 ◽

2004 ◽

Author(s):

R. Drechsler

Keyword(s):

Formal Verification ◽

System Level

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Prototyping with a bio-inspired recon .gurable chip

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004. ◽

10.1109/iwrsp.2004.1311123 ◽

2004 ◽

Cited By ~ 5

Author(s):

Y. Thoma ◽

E. Sanchez ◽

D. Roggen ◽

C. Hetherington ◽

J.-M. Moreno

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High level synthesis methodology from c to fpga used for a network protocol communication

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004. ◽

10.1109/iwrsp.2004.1311103 ◽

2004 ◽

Cited By ~ 2

Author(s):

M. Diaby ◽

M. Tuna ◽

J.-L. Desbarbieux ◽

F. Wajsburt

Keyword(s):

Network Protocol ◽

High Level Synthesis ◽

Synthesis Methodology ◽

High Level

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Formal specification and verification of embedded system with shared resources

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004. ◽

10.1109/iwrsp.2004.1311088 ◽

2004 ◽

Cited By ~ 1

Author(s):

Ki-Seok Bang ◽

Jin-Young Choi ◽

Sung-Ho Jang

Keyword(s):

Embedded System ◽

Formal Specification ◽

Shared Resources ◽

Formal Specification And Verification ◽

Specification And Verification

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Rapid software prototyping using visual language techniques

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004. ◽

10.1109/iwrsp.2004.1311106 ◽

2004 ◽

Cited By ~ 6

Author(s):

Kang Zhang ◽

Guang-Lei Song ◽

Jun Kong

Keyword(s):

Visual Language ◽

Software Prototyping

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Generation of distributed programs in their target execution environment

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004. ◽

10.1109/iwrsp.2004.1311107 ◽

2004 ◽

Author(s):

F. Gilliers ◽

J.-P. Velu ◽

F. Kordon

Keyword(s):

Distributed Programs ◽

Execution Environment

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ASET: a formal model for system emulation and verification

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004. ◽

10.1109/iwrsp.2004.1311090 ◽

2004 ◽

Author(s):

S. Bhattacharyya ◽

J. Bhattacharyya ◽

A.R. Chaudhuri

Keyword(s):

Formal Model

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Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Approaching interoperability from the bottom up:a lattice structure for the object-oriented method for interoperability (OOMI)

Automated hardware synthesis from formal specification using sat solvers

Network interface generation for mpsoc: from communication service requirements to rtl implementation

Towards formal verification on the system level

Prototyping with a bio-inspired recon .gurable chip

High level synthesis methodology from c to fpga used for a network protocol communication

Formal specification and verification of embedded system with shared resources

Rapid software prototyping using visual language techniques

Generation of distributed programs in their target execution environment

ASET: a formal model for system emulation and verification

Proceedings. 15th IEEE International Workshop on Rapid System Prototyping, 2004.
Latest Publications