Testing TAPed cores and wrapped cores with the same test access mechanism

Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001 ◽

10.1109/date.2001.915016 ◽

2002 ◽

Cited By ~ 5

Author(s):

M. Benabdenbi ◽

W. Maroufi ◽

M. Marzouki

Keyword(s):

Test Access Mechanism

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Multi-valued logic test access mechanism for test time and power reduction

2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS) ◽

10.1109/dtis.2015.7127351 ◽

2015 ◽

Cited By ~ 2

Author(s):

Amirreza Nekooei ◽

Zainalabedin Navabi

Keyword(s):

Power Reduction ◽

Test Time ◽

Test Access Mechanism

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Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism

2020 IEEE European Test Symposium (ETS) ◽

10.1109/ets48528.2020.9131560 ◽

2020 ◽

Cited By ~ 1

Author(s):

Mohamed Elshamy ◽

Giorgio Di Natale ◽

Antonios Pavlidis ◽

Marie-Minerve Louerat ◽

Haralampos-G. Stratigopoulos

Keyword(s):

Hardware Trojan ◽

Mixed Signal ◽

Test Access Mechanism

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Re-Examining the Use of Network-on-Chip as Test Access Mechanism

2008 Design, Automation and Test in Europe ◽

10.1109/date.2008.4484917 ◽

2008 ◽

Cited By ~ 3

Author(s):

Feng Yuan ◽

Lin Huang ◽

Qiang Xu

Keyword(s):

Network On Chip ◽

Test Access Mechanism ◽

On Chip

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On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools ◽

10.1109/dsd.2010.16 ◽

2010 ◽

Cited By ~ 5

Author(s):

Xiao Zhang ◽

Hans G. Kerkhoff ◽

Bart Vermeulen

Keyword(s):

Test Strategy ◽

Test Access Mechanism ◽

On Chip ◽

Many Core

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Contactless Test Access Mechanism for TSV-Based 3-D ICs Utilizing Capacitive Coupling

IEEE Transactions on Instrumentation and Measurement ◽

10.1109/tim.2015.2477240 ◽

2016 ◽

Vol 65 (1) ◽

pp. 88-95 ◽

Cited By ~ 5

Author(s):

Iftekhar Ibne Basith ◽

Rashid Rashidzadeh

Keyword(s):

Capacitive Coupling ◽

Test Access Mechanism

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A compression-driven test access mechanism design approach

Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004. ◽

10.1109/etsym.2004.1347617 ◽

2004 ◽

Cited By ~ 16

Author(s):

P.T. Gonciari ◽

B.M. Al-Hashimi

Keyword(s):

Mechanism Design ◽

Design Approach ◽

Test Access Mechanism

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Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism

Journal of Electronic Testing ◽

10.1007/s10836-010-5163-x ◽

2010 ◽

Vol 26 (4) ◽

pp. 453-464

Author(s):

Ardy van den Berg ◽

Pengwei Ren ◽

Erik Jan Marinissen ◽

Georgi Gaydadjiev ◽

Kees Goossens

Keyword(s):

Test Access Mechanism ◽

Bandwidth Analysis

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Test Access Mechanism for Multiple Identical Cores

2008 IEEE International Test Conference ◽

10.1109/test.2008.4700553 ◽

2008 ◽

Cited By ~ 21

Author(s):

G. Giles ◽

J. Wang ◽

A. Sehgal ◽

K.J. Balakrishnan ◽

J. Wingfield

Keyword(s):

Test Access Mechanism

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Test access mechanism for multiple identical cores

2009 International Test Conference ◽

10.1109/test.2009.5355560 ◽

2009 ◽

Cited By ~ 8

Author(s):

Grady Giles ◽

Jing Wang ◽

Anuja Sehgal ◽

Kedarnath J. Balakrishnan ◽

James Wingfield

Keyword(s):

Test Access Mechanism

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New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism

2010 15th IEEE European Test Symposium ◽

10.1109/etsym.2010.5512748 ◽

2010 ◽

Cited By ~ 1

Author(s):

Xiao Zhang ◽

Hans G. Kerkhoff ◽

Bart Vermeulen

Keyword(s):

Test Strategy ◽

Test Access Mechanism ◽

Many Core

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