A digital partial built-in self-test structure for a high performance automatic gain control circuit

2003 ◽  
Author(s):  
A. Lechner ◽  
J. Ferguson ◽  
A. Richardson ◽  
B. Hermes
Keyword(s):  
High Performance ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Control Circuit ◽  
Test Structure ◽  
Self Test ◽  
Built In Self Test

Design for Testability of High-Speed Advance Multipliers

2020 ◽  
pp. 175-190
Author(s):  
Suman Lata Tripathi
Keyword(s):  
High Speed ◽  
High Performance ◽  
Design For Testability ◽  
Online Testing ◽  
Efficient Design ◽  
Self Test ◽  
Built In Self Test ◽  
Work Done ◽  
Testing Work ◽  
Circuit Under Test

An efficient design for testability (DFT) has been a major thrust of area for today's VLSI engineers. A poorly designed DFT would result in losses for manufacturers with a considerable rework for the designers. BIST (built-in self-test), one of the promising DFT techniques, is rapidly modifying with the advances in technology as the device shrinks. The increasing complexities of the hardware have shifted the trend to include BISTs in high performance circuitry for offline as well as online testing. Work done here involves testing a circuit under test (CUT) with built in response analyser and vector generator with a monitor to control all the activities.

Sign in / Sign up

Export Citation Format

Share Document