Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

2002 ◽  
Author(s):  
Ki-Wook Kim ◽  
Seong-Ook Jung ◽  
P. Saxena ◽  
C.L. Liu ◽  
Sung-Mo Kang
Keyword(s):  
Threshold Voltage ◽  
Coupling Delay ◽  
Delay Optimization ◽  
Temporal Decorrelation ◽  
Dual Threshold Voltage

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

2003 ◽  
Vol 11 (5) ◽  
pp. 879-887 ◽  
Author(s):  
Ki-Wook Kim ◽  
Seong-Ook Jung ◽  
Taewhan Kim ◽  
P. Saxena ◽  
C.L. Liu ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Coupling Delay ◽  
Delay Optimization ◽  
Temporal Decorrelation ◽  
Dual Threshold Voltage

Spatial correlation-aware statistical dual-threshold voltage design of template-based asynchronous circuits

2018 ◽  
Vol 37 (3) ◽  
pp. 1189-1203
Author(s):  
Behnam Ghavami
Keyword(s):  
Low Power ◽  
Spatial Correlation ◽  
Threshold Voltage ◽  
High Performance ◽  
Process Variations ◽  
Low Power Design ◽  
Asynchronous Circuits ◽  
Asynchronous Circuit ◽  
Content Type ◽  
Dual Threshold Voltage

Purpose Power consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits. Design/methodology/approach In this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment. Findings Experimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits. Originality/value The proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

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