A unified DFT architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 compliant test access controllers

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) ◽

10.1109/dac.2001.935476 ◽

2002 ◽

Author(s):

B.I. Dervisoglu

Keyword(s):

Ieee 1149.1 ◽

Ieee P1500

Download Full-text

A unified DFT architecture for use with IEEE 1149.1 and VSIA/IEEE P1500 compliant test access controllers

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232) ◽

10.1145/378239.378280 ◽

2001 ◽

Cited By ~ 8

Author(s):

Bulent I. Dervisoglu

Keyword(s):

Ieee 1149.1 ◽

Ieee P1500

Download Full-text

A user programmable macrocell generator for the IEEE 1149.1 boundary scan standard interface port

Microprocessing and Microprogramming ◽

10.1016/0165-6074(92)90359-f ◽

1992 ◽

Vol 35 (1-5) ◽

pp. 493-500

Author(s):

Mark Royals ◽

Tassos Markas ◽

Nick Kanopoulos

Keyword(s):

Boundary Scan ◽

Standard Interface ◽

Ieee 1149.1

Download Full-text

On IEEE P1500’s Standard for Embedded Core Test

SOC (System-on-a-Chip) Testing for Plug and Play Test Automation - Frontiers in Electronic Testing ◽

10.1007/978-1-4757-6527-4_1 ◽

2002 ◽

pp. 1-19 ◽

Cited By ~ 3

Author(s):

Erik Jan Marinissen ◽

Rohit Kapur ◽

Maurice Lousberg ◽

Teresa McLaurin ◽

Mike Ricchetti ◽

...

Keyword(s):

Ieee P1500

Download Full-text

Toshiba IEEE 1149.1 (JTAG) development summary

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1991.242915 ◽

2002 ◽

Author(s):

J. Thomas

Keyword(s):

Ieee 1149.1

Download Full-text

Integration of IEEE 1149.1 with mixed ECL, TTL and differential logic signals

Proceedings ETC 93 Third European Test Conference ◽

10.1109/etc.1993.246575 ◽

2002 ◽

Cited By ~ 2

Author(s):

J. Andrews

Keyword(s):

Ieee 1149.1

Download Full-text

An implementation of IEEE 1149.1 to avoid timing violations and other practical in-compliance improvements

Proceedings. International Test Conference ◽

10.1109/test.2002.1041827 ◽

2003 ◽

Cited By ~ 1

Author(s):

D. Stang ◽

R. Dandapani

Keyword(s):

Ieee 1149.1 ◽

Timing Violations

Download Full-text

An IEEE 1149.1 compliant testability architecture with internal scan

Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors ◽

10.1109/iccd.1992.276309 ◽

2003 ◽

Cited By ~ 5

Author(s):

R.C. Zak ◽

J.V. Hill

Keyword(s):

Ieee 1149.1

Download Full-text

A chip to embedded system test process using IEEE 1149.1 boundary scan

Proceedings of ELECTRO '94 ◽

10.1109/electr.1994.472652 ◽

2002 ◽

Author(s):

J.E. Kadaras

Keyword(s):

Embedded System ◽

Boundary Scan ◽

Ieee 1149.1 ◽

Test Process

Download Full-text

Manufacturing defects testing of a multi-chip-module using IEEE 1149.1 boundary scan test and embedded built-in test software

AUTOTESTCON 93 ◽

10.1109/autest.1993.396355 ◽

2002 ◽

Author(s):

B.J. Round

Keyword(s):

Boundary Scan ◽

Manufacturing Defects ◽

Scan Test ◽

Ieee 1149.1 ◽

Boundary Scan Test

Download Full-text

An IEEE 1149.1 based voltmeter/oscilloscope in a chip

Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium ◽

10.1109/vtest.1993.313310 ◽

2002 ◽

Cited By ~ 7

Author(s):

L. Whetsel

Keyword(s):

Ieee 1149.1

Download Full-text