Low-voltage high-gain folded architecture operational amplifier

Author(s):  
Ketan J. Raut ◽  
R. V. Kshirsagar ◽  
A. C. Bhagali
Author(s):  
M.I.SUDHA RAYAPPA ◽  
V. SURENDRA BABU

This Thesis presents a design of the Folded-cascade operational amplifier which leads to high gain as compared to a normal cascade circuit. In this project; specifications of analog systems into op amp level net-lists of library components is studied and simulated using XILINX. As the power-supply voltages because of the technology improvement and it are desired to reduce power supply to minimize power dissipation, many challenges are faced by the analog designer. One is to keep noise level as possible. The op-amp must be designed to with the ever decreasing power supply voltages. As the power supply voltages begin to approach 2Vt, new technique and new op-amp topology like folded cascade should be used.


Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 74
Author(s):  
Na Bai ◽  
Xiaolong Li ◽  
Yaohua Xu

Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.


2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.


Author(s):  
Shuwen Guo ◽  
Xiaolong Zhao ◽  
Yongning He ◽  
Zijian Pan ◽  
Mingchao Yang ◽  
...  

Energies ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 800
Author(s):  
David Marroqui ◽  
Ausias Garrigós ◽  
Cristian Torres ◽  
Carlos Orts ◽  
Jose M. Blanes ◽  
...  

Many applications (electric vehicles, renewable energies, low-voltage DC grids) require simple, high-power density and low-current ripple-boost converters. Traditional step-up converters are limited when large transformation ratios are involved. In this work is proposed a step-up converter that brings together the characteristics of high gain, low ripple, and high-power density. From the converter proposal, a mathematical analysis of its operation is first performed, including its static transfer function, stress of components, and voltage and current ripples. Furthermore, it provides a design example for an application of Vin = 48 V to Vo = 270 V and 500 W. For its implementation, two different wide bandgap (WBG) semiconductor models have been used, hybrid GaN cascodes and SiC MOSFETs. Finally, the experimental results of the produced prototypes are shown, and the results are discussed.


2019 ◽  
Vol 71 ◽  
pp. 266-271 ◽  
Author(s):  
Donghui Lee ◽  
Kyung Gook Cho ◽  
Kyoung Hwan Seol ◽  
Sangho Lee ◽  
Soo-Hyung Choi ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document