A low-voltage, high-gain CMOS operational amplifier for switched-capacitor application in a digital 90nm CMOS process

2012 ◽  
Author(s):  
Atieh S. Khansarizadeh ◽  
S. Hassan Mirhosseini ◽  
Saeed Mehregan
Keyword(s):  
Operational Amplifier ◽  
Low Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Switched Capacitor

scholarly journals High-Gain Switched-Capacitor DC-DC Converter with Low Count of Switches and Low Voltage Stress of Switches

IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Robert Stala ◽  
Maciej Chojowski ◽  
Zbigniew Waradzyn ◽  
Andrzej Mondzik ◽  
Szymon Folmer ◽  
...  
Keyword(s):  
Low Voltage ◽  
High Gain ◽  
Switched Capacitor ◽  
Voltage Stress

scholarly journals DESIGN OF LOW VOLTAGE LOW POWER OPERATIONAL AMPLIFIER

2015 ◽  
pp. 257-261
Author(s):  
M.I.SUDHA RAYAPPA ◽  
V. SURENDRA BABU
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Operational Amplifier ◽  
Noise Level ◽  
Low Voltage ◽  
High Gain ◽  
Op Amp ◽  
Technology Improvement ◽  
Supply Voltages ◽  
Analog Systems

This Thesis presents a design of the Folded-cascade operational amplifier which leads to high gain as compared to a normal cascade circuit. In this project; specifications of analog systems into op amp level net-lists of library components is studied and simulated using XILINX. As the power-supply voltages because of the technology improvement and it are desired to reduce power supply to minimize power dissipation, many challenges are faced by the analog designer. One is to keep noise level as possible. The op-amp must be designed to with the ever decreasing power supply voltages. As the power supply voltages begin to approach 2Vt, new technique and new op-amp topology like folded cascade should be used.

scholarly journals A Low-Voltage, Ultra-Low-Power, High-Gain Operational Amplifier Design for Portable Wearable Devices

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 74
Author(s):  
Na Bai ◽  
Xiaolong Li ◽  
Yaohua Xu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Operational Amplifier ◽  
Low Voltage ◽  
Simulation Analysis ◽  
Supply Voltage ◽  
High Gain ◽  
Common Mode ◽  
Ultra Low Power ◽  
The Common

Based on the SMIC 0.13 um CMOS technology, this paper uses a 0.8 V supply voltage to design a low-voltage, ultra-low-power, high-gain, two-stage, fully differential operational amplifier. Through the simulation analysis, when the supply voltage is 0.8 V, the design circuit meets the ultra-low power consumption and also has the characteristic of high gain. The five-tube, fully differential, and common-source amplifier circuits provide the operational amplifier with high gain and large swing. Unlike the traditional common-mode feedback, this paper uses the output of the common-mode feedback as the bias voltage of the five-tube operational transconductance amplifier load, which reduces the design cost of the circuit; the structure involves self-cascoding composite MOS, which makes the common-mode feedback loop more sensitive. The frequency compensation circuit adopts Miller compensation technology with zero-pole separation, which increases the stability of the circuit. The input of the circuit uses the current mirror. A small reference current is chosen to reduce power consumption. A detailed performance simulation analysis of this operational amplifier circuit is carried out on the Cadence spectre platform. The open-loop gain of this operational amplifier is 74.1 dB, the phase margin is 61°, the output swing is 0.7 V, the common-mode rejection ratio is 109 dB, and the static power consumption is only 11.2 uW.

Design of High Gain CMOS Folded Cascode Operational Amplifier

2013 ◽  
Vol 389 ◽  
pp. 573-578
Author(s):  
Ming Xin Song ◽  
Yue Li ◽  
Meng Meng Xu
Keyword(s):  
Power Supply ◽  
Operational Amplifier ◽  
High Gain ◽  
Cmos Process ◽  
Phase Margin ◽  
Gain Bandwidth ◽  
Input Stage ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.

Sign in / Sign up

Export Citation Format

Share Document