Design for Testability Technique of Reversible Logic Circuits Based on Exclusive Testing

2017 IEEE 26th Asian Test Symposium (ATS) ◽

10.1109/ats.2017.54 ◽

2017 ◽

Author(s):

Joyati Mondal ◽

Debesh Kumar Das

Keyword(s):

Design For Testability ◽

Logic Circuits ◽

Reversible Logic

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Design-for-testability in reversible logic circuits based on bit-swapping

2015 IEEE 24th Asian Test Symposium (ATS) ◽

10.1109/ats.2015.8125669 ◽

2015 ◽

Author(s):

Joyati Mondal ◽

Debesh K. Das ◽

Bhargab B. Bhattacharya

Keyword(s):

Design For Testability ◽

Logic Circuits ◽

Reversible Logic

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Differential BiCMOS logic circuits: fault characterization and design-for-testability

Microelectronics Reliability ◽

10.1016/s0026-2714(97)87803-1 ◽

1997 ◽

Vol 37 (3) ◽

pp. 535-536

Keyword(s):

Design For Testability ◽

Logic Circuits ◽

Fault Characterization

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Bidirectional matrix-based algorithm for 4-qubit reversible logic circuits synthesis

IEEE Congress on Evolutionary Computation ◽

10.1109/cec.2010.5586417 ◽

2010 ◽

Author(s):

Dong Wang ◽

Hanwu Chen ◽

Wanning Zhu

Keyword(s):

Logic Circuits ◽

Reversible Logic

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Effective Hash-Based Algorithm for Reversible Logic Circuits Synthesis with Minimum Cost

2008 Fourth International Conference on Natural Computation ◽

10.1109/icnc.2008.191 ◽

2008 ◽

Author(s):

Zhiqiang Li ◽

Hanwu Chen ◽

Baowen Xu ◽

Xiaoyu Song ◽

Xiling Xue

Keyword(s):

Minimum Cost ◽

Logic Circuits ◽

Reversible Logic

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Analyzing Fault Models for Reversible Logic Circuits

2006 IEEE International Conference on Evolutionary Computation ◽

10.1109/cec.2006.1688609 ◽

2006 ◽

Cited By ~ 20

Author(s):

Jing Zhong ◽

J.C. Muzio

Keyword(s):

Logic Circuits ◽

Reversible Logic ◽

Fault Models

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Fault Tolerance in Reversible Logic Circuits and Quantum Cost Optimization

Computing and Informatics ◽

10.31577/cai_2020_5_1099 ◽

2020 ◽

Vol 39 (5) ◽

pp. 1099-1116

Author(s):

Kamaraj Arunachalam ◽

Marichamy Perumalsamy ◽

Kaviyashri K. Ponnusamy

Keyword(s):

Fault Tolerance ◽

Cost Optimization ◽

Logic Circuits ◽

Reversible Logic ◽

Quantum Cost

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An Overview of Different Approaches for Ternary Reversible Logic Circuits Synthesis Using Ternary Reversible Gates with Special Reference to Virtual Reality

Advances in Augmented Reality and Virtual Reality - Studies in Computational Intelligence ◽

10.1007/978-981-16-7220-0_6 ◽

2022 ◽

pp. 73-90

Author(s):

P. Mercy Nesa Rani ◽

Phrangboklang Lyngton Thangkhiew

Keyword(s):

Virtual Reality ◽

Special Reference ◽

Logic Circuits ◽

Reversible Logic

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Design of reversible logic based full adder in current-mode logic circuits

Microprocessors and Microsystems ◽

10.1016/j.micpro.2020.103100 ◽

2020 ◽

Vol 76 ◽

pp. 103100

Author(s):

S. Sharmila Devi ◽

V. Bhanumathi

Keyword(s):

Current Mode ◽

Full Adder ◽

Logic Circuits ◽

Reversible Logic ◽

Current Mode Logic

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A Survey on Adiabatic Logic Families for Implementing Reversible Logic Circuits

2018 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC) ◽

10.1109/iccic.2018.8782347 ◽

2018 ◽

Author(s):

R. M Bommi ◽

Raja S Selvakumar

Keyword(s):

Logic Circuits ◽

Reversible Logic ◽

Adiabatic Logic

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Design and Implementation of an Improved GEP Algorithm for Synthesis of Reversible Logic Circuits

Proceedings of the 9th International Conference on Computer and Automation Engineering - ICCAE '17 ◽

10.1145/3057039.3057060 ◽

2017 ◽

Author(s):

Shuguang Zhao ◽

Chaozheng Wang ◽

Kaixiang Xia

Keyword(s):

Logic Circuits ◽

Reversible Logic ◽

Design And Implementation

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