Post Silicon Debugging of Electrical Bugs Using Trace Buffers

2017 ◽  
Author(s):  
Kentaro Iwata ◽  
Amir Masoud Gharehbaghi ◽  
Mehdi B. Tahoori ◽  
Masahiro Fujita
Keyword(s):  
Silicon Debugging

A Silicon Debugging Methodology on Customer Prototype for Wafer Foundries

2012 ◽  
Author(s):  
Mai Zhihong ◽  
Ng Tsu Hau ◽  
Dawood M. Khalid ◽  
Tan Pik Kee ◽  
Jeffrey Lam
Keyword(s):  
Case Studies ◽  
Semiconductor Industry ◽  
Full Information ◽  
Limited Information ◽  
Ip Protection ◽  
First Case ◽  
Silicon Debugging ◽  
Failure Location ◽  
Device Chip ◽  
Latch Up

Abstract IP protection is of major importance for a semiconductor company and only limited information is made available for device debugging for the product outsourced to a foundry. In order to position ourselves better in the ever competitive semiconductor industry, with the consideration of IP protection, we have to provide the customers with the Si debugging capability and device/chip verification services in foundry. This paper explores the Si debugging methodology and technique in a foundry. Two case studies are presented and discussed. The first case illustrates the isolation of the failure location by InGaAs microscopy, upon which the failure was identified to be caused by a latch-up issue. In the second case, due to confidentiality considerations from the customer, full information could not be provided to the foundry for silicon debugging. The paper illustrates the ability to effectively debug a failure despite being constrained by limited information from the customer.

On a New Mechanism of Trigger Generation for Post-Silicon Debugging

2014 ◽  
Vol 63 (9) ◽  
pp. 2330-2342 ◽  
Author(s):  
M.H. Neishaburi ◽  
Zeljko Zilic
Keyword(s):  
Silicon Debugging

Re-using DFT logic for functional and silicon debugging test

2003 ◽  
Author(s):  
Xinli Gu ◽  
Weili Wang ◽  
K. Li ◽  
Heon Kim ◽  
S.S. Chung
Keyword(s):  
Silicon Debugging
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