2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)
Latest Publications

TOTAL DOCUMENTS

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9781424478057

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Fast and accurate UML State Chart modeling using TLM+ control flow abstraction

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2010.5496654 ◽

2010 ◽

Author(s):

Rainer Findenig ◽

Thomas Leitner ◽

Michael Veiten ◽

Wolfgang Ecker

Keyword(s):

Control Flow ◽

State Chart

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Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2010.5496668 ◽

2010 ◽

Cited By ~ 4

Author(s):

Bart Vermeulen ◽

Kees Goossens

Keyword(s):

Global State ◽

Systems On Chip ◽

On Chip

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Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2010.5496667 ◽

2010 ◽

Cited By ~ 13

Author(s):

O. Sarbishei ◽

Y. Pang ◽

K. Radecka

Keyword(s):

Fixed Point ◽

Arithmetic Circuits ◽

Linear Arithmetic

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A case study of Time-Multiplexed Assertion Checking for post-silicon debugging

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2010.5496657 ◽

2010 ◽

Cited By ~ 2

Author(s):

Ming Gao ◽

Kwang-Ting Cheng

Keyword(s):

Silicon Debugging

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HIFSuite: Tools for HDL code conversion and manipulation

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2010.5496665 ◽

2010 ◽

Cited By ~ 13

Author(s):

Nicola Bombieri ◽

Giuseppe Di Guglielmo ◽

Luigi Di Guglielmo ◽

Michele Ferrari ◽

Franco Fummi ◽

...

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Chairs' welcome message

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2010.5496672 ◽

2010 ◽

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Utility of transaction-level hardware models in refinement checking

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2010.5496650 ◽

2010 ◽

Author(s):

Yogesh Mahaj ◽

Sharad Malik

Keyword(s):

Refinement Checking ◽

Transaction Level

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2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2010.5496674 ◽

2010 ◽

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Static analysis of deadends in SVA constraints

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2010.5496656 ◽

2010 ◽

Author(s):

Ashvin Dsouza

Keyword(s):

Static Analysis

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Verification of real-time properties for Hardware-dependent Software

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT) ◽

10.1109/hldvt.2010.5496644 ◽

2010 ◽

Cited By ~ 1

Author(s):

Wolfgang Mueller ◽

Marcio F. da S. Oliveira ◽

Henning Zabel ◽

Markus Becker

Keyword(s):

Real Time

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2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Fast and accurate UML State Chart modeling using TLM+ control flow abstraction

Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks

Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks

A case study of Time-Multiplexed Assertion Checking for post-silicon debugging

HIFSuite: Tools for HDL code conversion and manipulation

Chairs' welcome message

Utility of transaction-level hardware models in refinement checking

Table of contents

Static analysis of deadends in SVA constraints

Verification of real-time properties for Hardware-dependent Software

Export Citation Format

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Fast and accurate UML State Chart modeling using TLM+ control flow abstraction

Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks

Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks

A case study of Time-Multiplexed Assertion Checking for post-silicon debugging

HIFSuite: Tools for HDL code conversion and manipulation

Chairs' welcome message

Utility of transaction-level hardware models in refinement checking

Table of contents

Static analysis of deadends in SVA constraints

Verification of real-time properties for Hardware-dependent Software

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)
Latest Publications