Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology

Author(s):  
Aibin Yan ◽  
Zhengfeng Huang ◽  
Xiangsheng Fang ◽  
Xiaolin Xu ◽  
Huaguo Liang
Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2124
Author(s):  
Egidio Ragonese ◽  
Claudio Nocera ◽  
Andrea Cavarra ◽  
Giuseppe Papotto ◽  
Simone Spataro ◽  
...  

This paper presents an extensive comparison of two 28-nm CMOS technologies, i.e., standard and mm-wave-optimized (i.e., thick metals and intermetal oxides) back-end-of-line (BEOL). The proposed comparison is carried out at both component and circuit level by means of a quantitative analysis of the actual performance improvements due to the adoption of a mm-wave-optimized BEOL. To this end, stand-alone transformer performance is first evaluated and then a complete mm-wave macroblock is investigated. A 77-GHz down-converter for frequency modulated continuous wave (FMCW) long-range/medium range (LR/MR) radar applications is exploited as a testbench. For the first time, it is demonstrated that thicker metals and intermetal oxides do not guarantee significant improvements at mm-wave frequencies and a standard (low-cost) BEOL is competitive in comparison with more complex (expensive) ones.


2012 ◽  
Vol 2012 ◽  
pp. 1-19 ◽  
Author(s):  
Xiaofang Hu ◽  
Shukai Duan ◽  
Lidan Wang

Chaotic Neural Network, also denoted by the acronym CNN, has rich dynamical behaviors that can be harnessed in promising engineering applications. However, due to its complex synapse learning rules and network structure, it is difficult to update its synaptic weights quickly and implement its large scale physical circuit. This paper addresses an implementation scheme of a novel CNN with memristive neural synapses that may provide a feasible solution for further development of CNN. Memristor, widely known as the fourth fundamental circuit element, was theoretically predicted by Chua in 1971 and has been developed in 2008 by the researchers in Hewlett-Packard Laboratory. Memristor based hybrid nanoscale CMOS technology is expected to revolutionize the digital and neuromorphic computation. The proposed memristive CNN has four significant features: (1) nanoscale memristors can simplify the synaptic circuit greatly and enable the synaptic weights update easily; (2) it can separate stored patterns from superimposed input; (3) it can deal with one-to-many associative memory; (4) it can deal with many-to-many associative memory. Simulation results are provided to illustrate the effectiveness of the proposed scheme.


2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.


Proceedings ◽  
2019 ◽  
Vol 2 (13) ◽  
pp. 751
Author(s):  
Bart Vereecke ◽  
Els Van Besien ◽  
Deniz Sabuncuoglu Tezcan ◽  
Nick Spooren ◽  
Nicolaas Tack ◽  
...  

Recent developments in multispectral cameras have demonstrated how compact and low-cost spectral sensors can be made by monolithically integrating filters on top of commercially available image sensors. In this paper, the fabrication of a RGB + NIR variation to such a single-chip imaging system is described, including the integration of a metallic shield to minimize crosstalk, and two interference filters: a NIR blocking filter, and a NIR bandpass filter. This is then combined with standard polymer based RGB colour filters. Fabrication of this chip is done in imec’s 200 mm cleanroom using standard CMOS technology, except for the addition of RGB colour filters and microlenses, which is outsourced.


2020 ◽  
Vol 20 (16) ◽  
pp. 8956-8964
Author(s):  
Mihir Gupta ◽  
Sybren Santermans ◽  
Bert Du Bois ◽  
Rita Vos ◽  
Simone Severi ◽  
...  

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