A Cost-Effective Scheme for Network-on-Chip Router and Interconnect Testing

Author(s):  
Dong Xiang
2021 ◽  
Vol 16 (2) ◽  
pp. 1-11
Author(s):  
Gustavo Lima ◽  
Diana Adamatti ◽  
Eduardo Brião ◽  
Cristina Meinhardt ◽  
Odorico Machado Mendizabal

Integrated systems have incorporated a variety of functionalities within the same chip, requiring on-chip communication mainly based on the Network-on-Chip (NoC) design paradigm. Complex systems may impose strict requirements concerning performance, power and reliability. Thus, the choice of proper routing algorithms to the on-chip communication for NoCs merits special attention. To assist designers to adjust communication parameters, implement routing algorithms, and check system correctness, simulators become powerful and cost-effective solutions. This article explores Multi-Agent System to develop a high level abstraction NoC simulation environment. The simulator allows designers to evaluate routing algorithms, test alternative configurations and message formats. The simulation provides important measurementssuch as rate of utilization of routers, network contention and delay in sending messages. As a case study, the XY and WF routing algorithms were modeled and analyzed. Results highlight the pros and cons of each algorithm, and outline the simulator overall performance.


Author(s):  
Rimpy Bishnoi ◽  
Vijay Laxmi ◽  
Manoj Singh Gaur ◽  
Radi Husin Bin Ramlee ◽  
Mark Zwolinski

Author(s):  
Farrukh Mehmood ◽  
Naveed Khan Baloch ◽  
Fawad Hussain ◽  
Waqar Amin ◽  
M. Shamim Hossain ◽  
...  

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