Worst-Case Critical-Path Delay Analysis Considering Power-Supply Noise

2013 ◽  
Author(s):  
Fang Bao ◽  
Mohammad Tehranippor ◽  
Harry Chen
Keyword(s):  
Power Supply ◽  
Critical Path ◽  
Delay Analysis ◽  
Path Delay ◽  
Power Supply Noise ◽  
Worst Case ◽  
Critical Path Delay ◽  
Supply Noise

Estimating Power Supply Noise and its impact on path delay

2012 ◽  
Author(s):  
Sushmita Kadiyala Rao ◽  
Chaitra Sathyanarayana ◽  
Ajay Kallianpur ◽  
Ryan Robucci ◽  
Chintan Patel
Keyword(s):  
Power Supply ◽  
Path Delay ◽  
Power Supply Noise ◽  
Supply Noise

Power Supply Noise Analysis Using Neural Network and Genetic Algorithm Based on Automatic Test Equipment

2003 ◽  
Author(s):  
Eric Liau ◽  
Doris Schmitt-Landsiedel
Keyword(s):  
Genetic Algorithm ◽  
Power Supply ◽  
Noise Analysis ◽  
Test Equipment ◽  
Power Supply Noise ◽  
Automatic Test Equipment ◽  
Automatic Test ◽  
Worst Case ◽  
Novel Approach ◽  
Supply Noise

Abstract Power supply noise (PSN) is becoming more severe as technology scales, and can cause signal distortion and increase gate delay. This can further result in improper circuit operation. In this paper, we propose a novel approach based on ATE (automatic test equipment) that teaches neural networks (NN) to correctly classify a set of worst case input patterns with respect to the maximum instantaneous current. This can be thought of as a learning behavior of chip power consumption change due to different input patterns. Then a genetic algorithm (GA) was applied to further optimize this set of NN worst case patterns. A final set of worst case patterns were expected to detect a small critical sequence of high switching currents that was directly related to the worst case power supply noise. This novel diagnosis approach can efficiently identify the defective design or weakness due to PSN as well as locate the defect or weaknesses within the design.

The Calculation and Anticipation Unit for Floating-Point Addition

2015 ◽  
Vol 24 (03) ◽  
pp. 1550029
Author(s):  
Linghao Li ◽  
Zhibiao Shao
Keyword(s):  
Critical Path ◽  
Floating Point ◽  
Double Precision ◽  
Path Delay ◽  
Worst Case ◽  
Critical Path Delay ◽  
Core Module ◽  
Area Occupation ◽  
The Individual ◽  
Open Core

Most recent microprocessors present multiple special functional units to optimize their performance. In this paper, a new functional unit called the calculation and anticipation (C&A) unit is presented for the IEEE 754 standard floating-point adder (FPA) that is the most important and frequently used calculation part for both modern CPUs and GPUs. C&A unit parallelize rounding step and readjustment step, which are known as the time-consuming steps for floating-point addition with significand addition. Therefore it reduces FPA critical path delay enormously, and even more decreases a little FPA area occupation. The synthesis results show that the double-precision FPA with C&A unit takes about 17.17% improvement in the critical path delay, while saves about 8.32% area than the conventional one. It takes 5.90% advantage in area and 19.58% improvement in the worst case delay than the double-precision FPA from the Open Core module "fpu_double" (rev 14 2010-02-13) synthesized in the same 0.13-μm CMOS bulk. Furthermore, comparing with the two-path double-precision FPA synthesized using LSI Logic's gflxp 0.11-μm CMOS library, it takes about 4.30% advantage in the critical path delay, and saves almost one-third area in the number of the individual cells.

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