Reduced-Complexity Transition-Fault Test Generation for Non-scan Circuits through High-Level Mutant Injection

2012 IEEE 21st Asian Test Symposium ◽

10.1109/ats.2012.47 ◽

2012 ◽

Cited By ~ 2

Author(s):

Valerio Guarnieri ◽

Franco Fummi ◽

Krishnendu Chakrabarty

Keyword(s):

Test Generation ◽

Transition Fault ◽

Reduced Complexity ◽

High Level ◽

Scan Circuits

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Reduced complexity test generation algorithms for transition fault diagnosis

2011 IEEE 29th International Conference on Computer Design (ICCD) ◽

10.1109/iccd.2011.6081382 ◽

2011 ◽

Cited By ~ 14

Author(s):

Yu Zhang ◽

Vishwani D. Agrawal

Keyword(s):

Fault Diagnosis ◽

Test Generation ◽

Transition Fault ◽

Reduced Complexity

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High Level Test Generation / SW based Embedded Test

14th Asian Test Symposium (ATS'05) ◽

10.1109/ats.2005.64 ◽

2005 ◽

Author(s):

P. Parvathala

Keyword(s):

Test Generation ◽

Embedded Test ◽

High Level

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High Level Test Generation via Process Composition

Designing Correct Circuits - Workshops in Computing ◽

10.1007/978-1-4471-3544-9_6 ◽

1991 ◽

pp. 99-119

Author(s):

Venkatesh Akella ◽

Ganesh Gopalakrishnan

Keyword(s):

Test Generation ◽

High Level ◽

Process Composition

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Using high-level primitives to speed up circuit partitioning in a mixed scan and non-scan environment for system level test generation

[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design ◽

10.1109/isvd.1991.185103 ◽

1991 ◽

Author(s):

S. Kode

Keyword(s):

Test Generation ◽

System Level ◽

Circuit Partitioning ◽

Speed Up ◽

High Level

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A new approach to test generation and test compaction for scan circuits

2003 Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2003.1253735 ◽

2003 ◽

Cited By ~ 12

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

New Approach ◽

Test Compaction ◽

Scan Circuits

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Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2010.2057459 ◽

2011 ◽

Vol 19 (10) ◽

pp. 1907-1911

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Quality Metric ◽

Transition Fault ◽

Full Scan ◽

Scan Circuits

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Synthesis of high-level requirements models for automatic test generation

Proceedings. Eighth Annual IEEE International Conference and Workshop On the Engineering of Computer Based Systems-ECBS 2001 ◽

10.1109/ecbs.2001.922408 ◽

2002 ◽

Cited By ~ 3

Author(s):

P. Gupta ◽

S.I. Cunning ◽

J.W. Rozenblit

Keyword(s):

Test Generation ◽

Automatic Test Generation ◽

Automatic Test ◽

High Level ◽

Requirements Models

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Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2013.2280170 ◽

2014 ◽

Vol 22 (9) ◽

pp. 1968-1979 ◽

Cited By ~ 6

Author(s):

Dong Xiang ◽

Wenjie Sui ◽

Boxue Yin ◽

Kwang-Ting Cheng

Keyword(s):

Test Generation ◽

Fault Testing ◽

Transition Fault ◽

Compact Test

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High-level test generation for VLSI

Computer ◽

10.1109/2.25379 ◽

1989 ◽

Vol 22 (4) ◽

pp. 16-24 ◽

Cited By ~ 6

Author(s):

D. Bhattacharya ◽

B.T. Murray ◽

J.P. Hayes

Keyword(s):

Test Generation ◽

High Level

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Test Generation and Evaluation from High-Level Properties for Common Criteria Evaluations -- The TASCCC Testing Tool

2013 IEEE Sixth International Conference on Software Testing, Verification and Validation ◽

10.1109/icst.2013.60 ◽

2013 ◽

Cited By ~ 2

Author(s):

Frederic Dadeau ◽

Kalou Cabrera Castillos ◽

Yves Ledru ◽

Taha Triki ◽

German Vega ◽

...

Keyword(s):

Test Generation ◽

Common Criteria ◽

Testing Tool ◽

High Level

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