Test power is one of the most challenges faced by Integrated Circuits. The author proposes a general scan chain architecture called Representative Scan (RS). It transforms the scan cells of conventional scan chain or sub-chain into circular shift registers and a representative flip-flop is chosen for each circular shift register, these representative flip-flops are connected serially to setup into the RS architecture. Thus, test data shifting path is shortened, then the switching activity is reduced in the shifting operates. The proposed scan architecture has the similar test power with the multiple scan chain, and only needs same test pins with single scan chain without added test pins. The experimental results show that the proposed scan architecture achieves very low shifting power. For benchmark circuits of ISCAS89, the shifting power of the best architecture of RS is only 0.53%–13.59% of the conventional scan. Especially for S35932, the shifting power on mintest test set is only 0.53% of the corresponding conventional scan. Compared with the conventional scan, the RS only needs to add a multiplexer for each scan cells, and the hardware cost is not high.
Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives