2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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9781538683989

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Efficient Non-Binary Hamming Codes for Limited Magnitude Errors in MLC PCMs

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2018.8602848 ◽

2018 ◽

Cited By ~ 1

Author(s):

Abhishek Das ◽

Nur A. Touba

Keyword(s):

Hamming Codes

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MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2018.8602934 ◽

2018 ◽

Author(s):

Ludovica Bozzoli ◽

Luca Sterpone

Keyword(s):

On Line ◽

Testing Approach ◽

Embedded Memories

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State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2018.8602984 ◽

2018 ◽

Author(s):

Markus Schutz ◽

Andreas Steininger ◽

Florian Huemer ◽

Jakob Lechner

Keyword(s):

Coarse Grain ◽

Partial Reconfiguration ◽

State Recovery

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45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2018.8602981 ◽

2018 ◽

Cited By ~ 1

Author(s):

Vishal Gupta ◽

Saurabh Khandelwal ◽

Jimson Mathew ◽

Marco Ottavi

Keyword(s):

Access Control ◽

Low Leakage

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Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep Processors

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2018.8602982 ◽

2018 ◽

Cited By ~ 3

Author(s):

A. Floridia ◽

E. Sanchez

Keyword(s):

Test Strategy ◽

On Line ◽

Self Test ◽

Dual Core

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Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2018.8602935 ◽

2018 ◽

Cited By ~ 3

Author(s):

Naixing Wang ◽

Irith Pomeranz ◽

Brady Benware ◽

M. Enamul Amyeen ◽

Srikanth Venkataraman

Keyword(s):

Multiple Defect ◽

Defect Diagnosis

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A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2018.8602971 ◽

2018 ◽

Cited By ~ 1

Author(s):

Alexandre Coelho ◽

Amir Charif ◽

Nacer-Eddine Zergainoh ◽

Raoul Velazco

Keyword(s):

Fault Tolerant ◽

Networks On Chip ◽

Routing Scheme ◽

On Chip ◽

3D Networks

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Threshold Voltage Extraction Using Static NBTI Aging

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2018.8602814 ◽

2018 ◽

Author(s):

Puneet Ramesh Savanur ◽

Spyros Tragoudas

Keyword(s):

Threshold Voltage

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Physics-Informed Machine Learning for DRAM Error Modeling

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2018.8602983 ◽

2018 ◽

Cited By ~ 1

Author(s):

Elisabeth Baseman ◽

Nathan Debardeleben ◽

Sean Blanchard ◽

Juston Moore ◽

Olena Tkachenko ◽

...

Keyword(s):

Machine Learning ◽

Error Modeling

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Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2018.8602841 ◽

2018 ◽

Cited By ~ 1

Author(s):

Yuta Yamamoto ◽

Kazuteru Namba

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2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Efficient Non-Binary Hamming Codes for Limited Magnitude Errors in MLC PCMs

MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories

State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration

45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control

Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep Processors

Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests

A Runtime Fault-Tolerant Routing Scheme for Partially Connected 3D Networks-on-Chip

Threshold Voltage Extraction Using Static NBTI Aging

Physics-Informed Machine Learning for DRAM Error Modeling

Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
Latest Publications