XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults

2008 ◽  
Author(s):  
Sunghoon Chun ◽  
Yongjoon Kim ◽  
Taejin Kim ◽  
Myung-Hoon Yang ◽  
Sungho Kang
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Efficient Test

scholarly journals An Efficient Test Pattern Generation Scheme for an On Chip BIST

VLSI Design ◽  
2001 ◽  
Vol 12 (4) ◽  
pp. 551-562 ◽  
Author(s):  
B. K. S. V. L. Varaprasad ◽  
L. M. Patnaik ◽  
H. S. Jamadagni ◽  
V. K. Agrawal
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Pattern ◽  
Circuit Simulation ◽  
Cost Effective ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Space Applications ◽  
Efficient Test ◽  
On Chip

Testing and power consumption are becoming two critical issues in VLSI design due to the growing complexity of VLSI circuits and remarkable success and growth of low power applications (viz. portable consumer electronics and space applications). On chip Built In Self Test (BIST) is a cost-effective test methodology for highly complex VLSI devices like Systems On Chip. This paper deals with cost-effective Test Pattern Generation (TPG) schemes in BIST. We present a novel methodology based on the use of a suitable Linear Feedback Shift Register (LFSR) which cycles through the required sequences (test vectors) aiming at a desired fault coverage causing minimum circuit toggling and hence low power consumption while testing. The proposed technique uses circuit simulation data for modeling. We show how to identify the LFSR using graph theory techniques and compute its feedback coefficients (i.e., its characteristic polynomial) for realization of a Test Pattern Generator.

scholarly journals Efficient Test Application for Core-Based Systems Using Twisted-Ring Counters

VLSI Design ◽  
2001 ◽  
Vol 12 (4) ◽  
pp. 475-486
Author(s):  
Anshuman Chandra ◽  
Krishnendu Chakrabarty ◽  
Mark C. Hansen
Keyword(s):  
Test Pattern ◽  
Pattern Generation ◽  
Test Pattern Generation ◽  
Testing Time ◽  
Automatic Test Pattern Generation ◽  
Test Quality ◽  
Efficient Test ◽  
Test Application ◽  
Test Sets ◽  
Test Architecture

We present novel test set encoding and pattern decompression methods for core-based systems. These are based on the use of twisted-ring counters and offer a number of important advantages–significant test compression (over 10X in many cases), less tester memory and reduced testing time, the ability to use a slow tester without compromising test quality or testing time, and no performance degradation for the core under test. Surprisingly, the encoded test sets obtained from partially-specified test sets (test cubes) are often smaller than the compacted test sets generated by automatic test pattern generation programs. Moreover, a large number of patterns are applied test-per-clock to cores, thereby increasing the likelihood of detecting non-modeled faults. Experimental results for the ISCAS benchmark circuits demonstrate that the proposed test architecture offers an attractive solution to the problem of achieving high test quality and low testing time with relatively slower, less expensive testers.

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