Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction

2005 ◽  
Author(s):  
Y. Higami ◽  
S. Kajihara ◽  
S.-y. Kobayashi ◽  
Y. Takamatsu
Keyword(s):  
Power Reduction ◽  
Sequential Circuits ◽  
Test Length

scholarly journals POWER REDUCTION BY GUARDED EVALUATION CONSIDERING LOGIC ARCHITECTURE AND USING CLOCK GATING

2015 ◽  
pp. 233-238
Author(s):  
G. SURESH ◽  
A.RAM KUMAR
Keyword(s):  
Digital Circuits ◽  
Power Reduction ◽  
Leakage Power ◽  
Sequential Circuits ◽  
Reduction Technique ◽  
Digital Design ◽  
Combinational Circuits ◽  
Clock Gating ◽  
Dynamic Power ◽  
Circuit Input

In this paper, guarded evaluation is a dynamic power reduction technique by identifying sub circuits inputs and kept constant at specific times during circuit operation. In certain condition, some signals within the digital design are not observable at output. So make such signals as guarded (constant). There by reducing the dynamic power. Here we apply this technique for all digital circuits. The problem here is to find conditions under which a sub circuit input can be held constant with disturbing the main circuit functionally (correctness). Here we propose a solution for discovering the gating inputs based on inverting and non-inverting methods. By including “clock gating” we still reduce the dynamic power and leakage power especially for sequential circuits and also used to some small combinational circuits.

LEAKAGE POWER REDUCTION USING MULTI MODAL DRIVEN HIERARCHICAL POWER MODE SWITCHES

2018 ◽  
Vol 6 (2) ◽  
pp. 1
Author(s):  
SEKHAR REDDY M. CHANDRA ◽  
REDDY P. RAMANA ◽  
◽  
Keyword(s):  
Power Reduction ◽  
Leakage Power ◽  
Power Mode

Methodology for an Operationally-Based Test Length Decision

1997 ◽  
Author(s):  
Donald P. Gaver ◽  
Patricia A. Jacobs
Keyword(s):  
Test Length

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

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