Test generation for fault isolation in analog circuits using behavioral models

2002 ◽  
Author(s):  
S. Cherubal ◽  
A. Chatterjee
Keyword(s):  
Analog Circuits ◽  
Test Generation ◽  
Fault Isolation ◽  
Behavioral Models

Multi-Rider Optimization-Based Neural Network for Fault Isolation in Analog Circuits

2020 ◽  
pp. 2150048
Author(s):  
D. Binu ◽  
B. S. Kariyappa
Keyword(s):  
Neural Network ◽  
Analog Circuits ◽  
Minimum Mean Square Error ◽  
Predictive Coding ◽  
Principal Component ◽  
Power Converter ◽  
Fault Isolation ◽  
Linear Predictive Coding ◽  
Fault Dictionary ◽  
Area Of Interest

Fault isolation in electronic circuits is a trending area of interest as analog circuits find valuable application in industry. The failures in circuit systems cause severe issues in the normal functioning of the system that insists on the need for an automatic method of fault isolation in analog circuits. Literature conveys the issues associated with the fault isolation and hence, to address the severity of the faults, a novel model is proposed to isolate the fault causing component in the circuit. The proposed Multi-Rider Optimization-based Neural Network (M-RideNN) isolates the faulty part of the circuit from the fault-free areas such that the fault diagnosis is structured in an effective way. The fault isolation is progressed as four major steps such as establishing the fault dictionary, signal normalization using Linear Predictive Coding (LPC), effective dimensional reduction methodology using Probabilistic Principal Component Analysis (PPCA), and fault isolation using the proposed M-RideNN classifier. Finally, the experimentation using three circuits, namely Triangular Wave Generator (TWG), Bipolar Transistor Amplifier (BTA), differentiator (DIF), and an application circuit, Solar Power Converter (SPC), proves that the proposed M-RideNN classifier offers better classification accuracy of 93.18% with a minimum Mean Square Error (MSE) of 0.0682.

Optimization-based multifrequency test generation for analog circuits

1996 ◽  
Vol 9 (1-2) ◽  
pp. 59-73 ◽  
Author(s):  
A. Abderrahman ◽  
B. Kaminska ◽  
E. Cerny
Keyword(s):  
Analog Circuits ◽  
Test Generation

scholarly journals Test Generation Algorithm for Fault Detection of Analog Circuits Based on Extreme Learning Machine

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Jingyu Zhou ◽  
Shulin Tian ◽  
Chenglin Yang ◽  
Xuelong Ren
Keyword(s):  
Extreme Learning Machine ◽  
Analog Circuits ◽  
Test Generation ◽  
Cost Effective ◽  
Fault Classification ◽  
The Novel ◽  
Analog Device ◽  
Generation Algorithm ◽  
New Process ◽  
Learning Machine

This paper proposes a novel test generation algorithm based on extreme learning machine (ELM), and such algorithm is cost-effective and low-risk for analog device under test (DUT). This method uses test patterns derived from the test generation algorithm to stimulate DUT, and then samples output responses of the DUT for fault classification and detection. The novel ELM-based test generation algorithm proposed in this paper contains mainly three aspects of innovation. Firstly, this algorithm saves time efficiently by classifying response space with ELM. Secondly, this algorithm can avoid reduced test precision efficiently in case of reduction of the number of impulse-response samples. Thirdly, a new process of test signal generator and a test structure in test generation algorithm are presented, and both of them are very simple. Finally, the abovementioned improvement and functioning are confirmed in experiments.

Using Electrical Fault Isolation and Characterization to Improve the Effectiveness of Physical Fault Isolation Techniques for Analog Circuits

2017 ◽  
Author(s):  
Jim Douglass ◽  
Sohrab Pourmand
Keyword(s):  
Induced Resistance ◽  
Analog Circuits ◽  
Fault Isolation ◽  
Optical Beam ◽  
Resistance Change ◽  
Isolation Techniques ◽  
Isolation And Characterization ◽  
Lock In

Abstract This paper shows that by combining electrical fault isolation and characterization by microprobing with physical fault isolation techniques both what is wrong with the circuit and where the defect is located can be determined with less microprobing and more safety from electrical recovery. In the first example, the unit was powered up using the optical beam induced resistance change (OBIRCH) supply, and OBIRCH was performed to determine if there were OBIRCH site differences between the good part and the return. The second example uses a combination of electrical fault isolation and characterization with microprobing and the physical fault isolation tool of lock in thermography (LIT). With these two examples, it has been shown that the use of electrical fault isolation and microprobing can be used to enhance the physical fault isolation tools of OBIRCH and LIT.

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