Fast Asynchronous Shift Register for Bit-Serial Communication

2006 ◽  
Author(s):  
R. Dobkin ◽  
R. Ginosar ◽  
A. Kolodny
Keyword(s):  
Serial Communication ◽  
Shift Register ◽  
Bit Serial

High density bit-serial FPGA with LUT embedding shift register function

2003 ◽  
Author(s):  
T. Isshiki ◽  
A. Ohta ◽  
T. Watanabe ◽  
T. Nakada ◽  
K. Akahane ◽  
...  
Keyword(s):  
High Density ◽  
Shift Register ◽  
Bit Serial

Transforming bit-serial communication circuits into fast parallel VLSI implementations

1988 ◽  
Vol 23 (2) ◽  
pp. 549-557 ◽  
Author(s):  
D.M. Lewis ◽  
B.W. Thomson ◽  
P.I.P. Boulton ◽  
E.S. Lee
Keyword(s):  
Serial Communication ◽  
Communication Circuits ◽  
Bit Serial

scholarly journals Design and Implementation of Efficient 8-Bit SIPO Shift Register

2020 ◽  
Vol 22 (12) ◽  
Author(s):  
Sandeep Kakde ◽  
◽  
Rajesh Thakare S ◽  
Shailesh Kamble ◽  
Umakant Mandawkar ◽  
...  
Keyword(s):  
Single Phase ◽  
Digital Circuits ◽  
Shift Register ◽  
Design Constraints ◽  
Flip Flop ◽  
Main Design ◽  
Design And Implementation ◽  
Analog And Digital Circuits ◽  
Conventional Type ◽  
Bit Serial

Area and power are main design constraints in analog and digital circuits. In this paper, a low-power 8-bit shift register is implemented by using true phase single clock (TSPC) D- flip flop which is based on single clock and two clocked transistors. The proposed design successfully solves the long discharge path problem which is bound to occur in conventional type of D-Flip Flop. This paper describes 8 bit serial in parallel out (SIPO) shift register using True Single-Phase Clock(TSPC) technique which reduces an area in terms of transistor count by 85.29%.

Development of Bit-Serial RSFQ Microprocessors Integrated with Shift-Register-Based Random Access Memories

2015 ◽  
Author(s):  
Masamitsu Tanaka ◽  
Kensuke Takata ◽  
Takahiro Kawaguchi ◽  
Yuki Ando ◽  
Nobuyuki Yoshikawa ◽  
...  
Keyword(s):  
Random Access ◽  
Shift Register ◽  
Bit Serial
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