Design and Implementation of Efficient 8-Bit SIPO Shift Register

Area and power are main design constraints in analog and digital circuits. In this paper, a low-power 8-bit shift register is implemented by using true phase single clock (TSPC) D- flip flop which is based on single clock and two clocked transistors. The proposed design successfully solves the long discharge path problem which is bound to occur in conventional type of D-Flip Flop. This paper describes 8 bit serial in parallel out (SIPO) shift register using True Single-Phase Clock(TSPC) technique which reduces an area in terms of transistor count by 85.29%.