High density bit-serial FPGA with LUT embedding shift register function

Author(s):  
T. Isshiki ◽  
A. Ohta ◽  
T. Watanabe ◽  
T. Nakada ◽  
K. Akahane ◽  
...  
Author(s):  
Sandeep Kakde ◽  
◽  
Rajesh Thakare S ◽  
Shailesh Kamble ◽  
Umakant Mandawkar ◽  
...  

Area and power are main design constraints in analog and digital circuits. In this paper, a low-power 8-bit shift register is implemented by using true phase single clock (TSPC) D- flip flop which is based on single clock and two clocked transistors. The proposed design successfully solves the long discharge path problem which is bound to occur in conventional type of D-Flip Flop. This paper describes 8 bit serial in parallel out (SIPO) shift register using True Single-Phase Clock(TSPC) technique which reduces an area in terms of transistor count by 85.29%.


Author(s):  
Masamitsu Tanaka ◽  
Kensuke Takata ◽  
Takahiro Kawaguchi ◽  
Yuki Ando ◽  
Nobuyuki Yoshikawa ◽  
...  

1972 ◽  
Author(s):  
V. Sadagopan ◽  
M. Hatzakis ◽  
K. Y. Ahn ◽  
T. S. Plaskett ◽  
L. L. Rosier ◽  
...  
Keyword(s):  

Author(s):  
S. McKernan ◽  
C. B. Carter ◽  
D. Bour ◽  
J. R. Shealy

The growth of ternary III-V semiconductors by organo-metallic vapor phase epitaxy (OMVPE) is widely practiced. It has been generally assumed that the resulting structure is the same as that of the corresponding binary semiconductors, but with the two different cation or anion species randomly distributed on their appropriate sublattice sites. Recently several different ternary semiconductors including AlxGa1-xAs, Gaxln-1-xAs and Gaxln1-xP1-6 have been observed in ordered states. A common feature of these ordered compounds is that they contain a relatively high density of defects. This is evident in electron diffraction patterns from these materials where streaks, which are typically parallel to the growth direction, are associated with the extra reflections arising from the ordering. However, where the (Ga,ln)P epilayer is reasonably well ordered the streaking is extremely faint, and the intensity of the ordered spot at 1/2(111) is much greater than that at 1/2(111). In these cases it is possible to image relatively clearly many of the defects found in the ordered structure.


Author(s):  
L. Mulestagno ◽  
J.C. Holzer ◽  
P. Fraundorf

Due to the wealth of information, both analytical and structural that can be obtained from it TEM always has been a favorite tool for the analysis of process-induced defects in semiconductor wafers. The only major disadvantage has always been, that the volume under study in the TEM is relatively small, making it difficult to locate low density defects, and sample preparation is a somewhat lengthy procedure. This problem has been somewhat alleviated by the availability of efficient low angle milling.Using a PIPS® variable angle ion -mill, manufactured by Gatan, we have been consistently obtaining planar specimens with a high quality thin area in excess of 5 × 104 μm2 in about half an hour (milling time), which has made it possible to locate defects at lower densities, or, for defects of relatively high density, obtain information which is statistically more significant (table 1).


Sign in / Sign up

Export Citation Format

Share Document