Early Testable Addressable Logic (ETAL) Test Structure: Showcasing the use of an Alternate Logic Yield Learning Test Structure for Technology Development

2019 ◽  
Author(s):  
Ishtiaq Ahsan ◽  
Shahrukh Khan ◽  
Joerg Winkler ◽  
Kannan Sekar ◽  
Neerja Bawaskar ◽  
...  
Keyword(s):  
Technology Development ◽  
Test Structure ◽  
Yield Learning ◽  
Learning Test

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

MALTY––A memory test structure for analysis in the early phase of the technology development

2003 ◽  
Vol 43 (9-11) ◽  
pp. 1383-1387 ◽  
Author(s):  
Th. Nirschl ◽  
M. Ostermayr ◽  
A. Olbrich ◽  
D. Vietzke ◽  
M. Omer ◽  
...  
Keyword(s):  
Early Phase ◽  
Technology Development ◽  
Memory Test ◽  
Test Structure

Tristate Inverter Array: A New Technology Development Yield Learning Vehicle Complementing Traditional SRAM Arrays

2015 ◽  
Vol 28 (4) ◽  
pp. 474-479 ◽  
Author(s):  
Ishtiaq Ahsan ◽  
Carl Schiller ◽  
Fred Towler ◽  
Zhigang Song ◽  
Robert Wong ◽  
...  
Keyword(s):  
Technology Development ◽  
New Technology ◽  
Yield Learning

Logic Yield Learning Vehicle Failure Analysis in Technology Development

2012 ◽  
Author(s):  
Zhigang Song ◽  
Felix Beaudoin ◽  
Stephen Lucarini ◽  
Stephen Wu ◽  
Yunyu Wang ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Technology Development ◽  
Development Stage ◽  
Logic Circuits ◽  
Product Logic ◽  
Microelectronic Technology ◽  
Yield Learning ◽  
Weak Points ◽  
Product Manufacturing ◽  
Manufacturing Yield

Abstract With the microelectronic technology progresses in nanometer realm, like SRAM, logic circuits and structures are also becoming dense and more sensitive to process variation. Logic failures may have different root causes from SRAM failure. If these technology weak points for logic circuits are not detected and resolved during the technology development stage, they will greatly affect the product manufacturing yield ramp, leading to longer time of design to market. In this paper, we present a logic yield learning methodology based on an inline logic vehicle, which includes several scan chains of different latch types representative of product logic. Failure analysis for the low yield wafers had revealed several killer defects associated with logic circuits. A few examples of the systematic failures unique to logic circuits will be presented. In combination with SRAM yield learning, logic yield learning makes the technology development more robust thus improving manufacturability.

Early Inline Detection of Systematic Defects Using ATPG and Commonality Analysis on Product-Like Logic Yield Learning Vehicle

2013 ◽  
Author(s):  
Felix Beaudoin ◽  
Zhigang Song ◽  
Stephen Lucarini ◽  
Thomas F. Mechler ◽  
Stephen Wu ◽  
...  
Keyword(s):  
Technology Development ◽  
High Volume ◽  
The Novel ◽  
Front End ◽  
Yield Learning ◽  
Commonality Analysis ◽  
Test Flow ◽  
Development Phases ◽  
Soi Technology ◽  
Random Defect

Abstract This paper presents the successful use of the novel inline product-like logic vehicle (PATO) during the last technology development phases of IBM's 22nm SOI technology node. It provides information on the sequential PATO inline test flow, commonality analysis procedure, and commonality signature trending. The paper presents examples of systematic defects uniquely captured by the product-like back end of the line layout. Moreover, this complex logic vehicle also uncovered a rich Pareto of more than 20 types of systematic and random defect mechanisms across the front end of the line, the middle end of the line, and the back end of the line. And more importantly, the non-defect found rate was kept below 20%. This achievement was possible by: leveraging high volume inline test ATPG scan fail data through the novel commonality analysis approach; and selecting the highest ATPG confidence defects representing a known commonality signature to physical failure analysis.

Yield Learning Methodology in Early Technology Development

2007 ◽  
Author(s):  
Xu Ouyang ◽  
David Riggs ◽  
Ishtiaq Ahsan ◽  
Oliver D. Patterson ◽  
Dallas M. Lea ◽  
...  
Keyword(s):  
Technology Development ◽  
Yield Learning
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