Tristate Inverter Array: A new test structure that compliments traditional SRAM arrays as a yield learning vehicle

2014 ◽  
Author(s):  
Ishtiaq Ahsan ◽  
Carl Schiller ◽  
Zhigang Song ◽  
Robert Wong ◽  
David Clark ◽  
...  
Keyword(s):  
Test Structure ◽  
Yield Learning

Development of Test Structure for Variability Evaluation using Charge-Based Capacitance Measurement

2014 ◽  
Vol E97.C (11) ◽  
pp. 1117-1123 ◽  
Author(s):  
Katsuhiro TSUJI ◽  
Kazuo TERADA ◽  
Ryota KIKUCHI
Keyword(s):  
Test Structure ◽  
Capacitance Measurement

Classification of IC Process Deformation Characteristics Using Memory Fail Bitmaps

2004 ◽  
Author(s):  
T. Zanon ◽  
W. Maly
Keyword(s):  
Geometric Characterization ◽  
Deformation Characteristics ◽  
Analysis Study ◽  
Preliminary Results ◽  
Failure Patterns ◽  
Yield Learning ◽  
Sram Memory ◽  
Viable Approach ◽  
Ic Technology

Abstract Building a portfolio of deformations is the key step for building better defect models for the test and yield learning domain. A viable approach to achieve this goal is through geometric characterization and classification of failure patterns found on memory fail bitmaps. In this paper, we present preliminary results on how to build such a portfolio of deformations for an IC technology of interest based on a fail bitmap analysis study conducted on large, modern SRAM memory products.

Sub-20nm Device Voltage-Sensitive SRAM Characterization and Failure Analysis

2018 ◽  
Author(s):  
Seng Nguon Ting ◽  
Hsien-Ching Lo ◽  
Donald Nedeau ◽  
Aaron Sinnott ◽  
Felix Beaudoin
Keyword(s):  
Failure Analysis ◽  
High Performance ◽  
Yield Loss ◽  
Technology Development ◽  
High Density ◽  
High K ◽  
Yield Learning ◽  
Oxide Deposition ◽  
Edge Profile ◽  
High K Dielectric

Abstract With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

Advanced Scan Diagnosis Based Fault Isolation and Defect Identification for Yield Learning

2005 ◽  
Author(s):  
Chris Eddleman ◽  
Nagesh Tamarapalli ◽  
Wu-Tung Cheng
Keyword(s):  
Failure Analysis ◽  
Fault Location ◽  
Effective Means ◽  
Fault Isolation ◽  
Yield Enhancement ◽  
Yield Analysis ◽  
Isolation Techniques ◽  
Yield Learning ◽  
Time Required ◽  
Inspection Data

Abstract Yield analysis of sub-micron devices is an ever-increasing challenge. The difficulty is compounded by the lack of in-line inspection data as many companies adopt foundry or fab-less models for acquiring wafers. In this scenario, failure analysis is increasingly critical to help drive yields. Failure analysis is a process of fault isolation, or a method of isolating failures as precisely as possible followed by identification of a physical defect. As the number of transistors and metal layers increase, traditional fault isolation techniques are less successful at isolating a cause of failures. Costs are increasing due to the amount of time needed to locate the physical defect. One solution to the yield analysis problem is scan diagnosis based fault isolation. Previous scan diagnosis based techniques were limited with little information about the type of fault and confidence of diagnosis. With new scan diagnosis algorithms it is now possible to not only isolate, but to identify the type of fault as well as assigning a confidence ranking prior to any destructive analysis. This paper presents multiple case studies illustrating the application of scan diagnosis as an effective means to achieve yield enhancement. The advanced scan diagnostic tool used in this study provides information about the fault type as well as fault location. This information focuses failure analysis efforts toward a suspected defect, decreasing the cycle time required to determine root cause, as well as increasing the over all success rate.

Precise Localization of 28 nm via Chain Resistive Defect Using EBAC and Nanoprobing

2012 ◽  
Author(s):  
P. Larré ◽  
H. Tupin ◽  
C. Charles ◽  
R.H. Newton ◽  
A. Reverdy
Keyword(s):  
Electron Beam ◽  
Failure Analysis ◽  
Test Structure ◽  
Precise Localization ◽  
Isolation Method ◽  
Accurate Detection ◽  
Conventional Methods ◽  
Technology Nodes ◽  
Tem Lamella

Abstract As technology nodes continue to shrink, resistive opens have become increasingly difficult to detect using conventional methods such as AVC and PVC. The failure isolation method, Electron Beam Absorbed Current (EBAC) Imaging has recently become the preferred method in failure analysis labs for fast and highly accurate detection of resistive opens and shorts on a number of structures. This paper presents a case study using a two nanoprobe EBAC technique on a 28nm node test structure. This technique pinpointed the fail and allowed direct TEM lamella.

Backside FIB Device Modifications Through the BOX Layer of an SOI Device

2002 ◽  
Author(s):  
Jeffery P. Huynh ◽  
Joseph P. Shannon ◽  
Richard W. Johnson ◽  
Mike Santana ◽  
Thomas Y. Chu ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Oxide Layer ◽  
Cross Section ◽  
Test Structure ◽  
Ring Oscillator ◽  
Oscillator Circuit ◽  
Entire Process ◽  
Oscillator Frequency ◽  
Polysilicon Gate ◽  
Resistance Data

Abstract Modifications directly to a transistor’s source/drain and polysilicon gate through the backside of a SOI device were made. Contact resistance data was obtained by creating contacts through the buried oxide layer of a manufactured test structure. A ring oscillator circuit was modified and the shift in oscillator frequency was measured. Finally, cross section images of the FIB created contacts were presented in the paper to illustrate the entire process.

A Test Structure to Characterize Nano-Scale Ohmic Contacts in III-V MOSFETs

2014 ◽  
Vol 35 (2) ◽  
pp. 178-180 ◽  
Author(s):  
Wenjie Lu ◽  
Alex Guo ◽  
Alon Vardi ◽  
Jesus A. del Alamo
Keyword(s):  
Ohmic Contacts ◽  
Test Structure ◽  
Nano Scale

Modified sliding mode control of a seismic active mass damper system considering model uncertainties and input time delay

2016 ◽  
Vol 24 (6) ◽  
pp. 1051-1064 ◽  
Author(s):  
Mehdi Soleymani ◽  
Amir Hossein Abolmasoumi ◽  
Hasanali Bahrami ◽  
Arash Khalatbari-S ◽  
Elham Khoshbin ◽  
...  
Keyword(s):  
Structural Control ◽  
Sliding Mode ◽  
Test Structure ◽  
Dynamic State ◽  
Shake Table ◽  
Model Uncertainties ◽  
Actuator Dynamics ◽  
Active Structural Control ◽  
Mass Damper ◽  
Active Mass Damper

Model uncertainties and actuator delays are two factors that degrade the performance of active structural control systems. A new robust control system is proposed for control of an active tuned mass damper (AMD) in a high-rise building. The controller comprises a two-loop sliding model controller in conjunction with a dynamic state predictor. The sliding model controller is responsible for model uncertainties and the state predictor compensates for the time delays due to actuator dynamics and process delay. A reduced model that is validated against experimental data was constructed and equipped with an electro-mechanical AMD system mounted on the top storey. The proposed controller was implemented in the test structure and its performance under seismic disturbances was simulated using a seismic shake table. Moreover, robustness of the proposed controller was examined via variation of the test structure parameters. The shake table test results reveal the effectiveness of the proposed controller at tackling the simulated disturbances in the presence of model uncertainties and input delay.

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