Yield improvement and queue time relaxation at contact process

2016 ◽  
Author(s):  
Niti Garg ◽  
Philippe Helal ◽  
Pranesh Muralidhar ◽  
Stephen Crown ◽  
Vincent Sih ◽  
...  
Keyword(s):  
Contact Process ◽  
Yield Improvement ◽  
Time Relaxation

Contact Process Optimization for 40nm CMOS Yield Improvement

2013 ◽  
Vol 52 (1) ◽  
pp. 619-623
Author(s):  
Y. Lin ◽  
X.-P. Wang ◽  
L. Chen ◽  
C. J. Yang
Keyword(s):  
Process Optimization ◽  
Contact Process ◽  
Yield Improvement

Defect Snap Shot: Quick Isolation and Mapping of Interconnect Defects for Backend Yield Improvement

2004 ◽  
Author(s):  
Jenny Fan ◽  
Dave Mark
Keyword(s):  
Metal Layer ◽  
Single Layer ◽  
Yield Improvement ◽  
Test Methodology ◽  
Process Complexity

Abstract Metal interconnect defects have become a more serious yield detractor as backend process complexity has increased from a single layer to about 10 layers. This paper introduces a test methodology to monitor and localize the metal defects based on FPGA products. The test patterns are generated for each metal layer. The results not only indicate the severity of defects for each metal layer, but also accurately isolate open/short defects.

In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

2000 ◽  
Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Failure Mechanisms ◽  
Memory Devices ◽  
Line Defect ◽  
Yield Improvement ◽  
Electrical Test ◽  
Large Numbers ◽  
Improvement Process ◽  
Existing Data

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

BiCMOS Die Sort Yield Improvement from Isolation of a Localized Defect Mechanism and Precision TEM Cross Section

1997 ◽  
Author(s):  
J. Douglass ◽  
T. D. Myers ◽  
F. Tsai ◽  
R. Ketcheson ◽  
J. Errett
Keyword(s):  
Electron Microscopy ◽  
Cross Section ◽  
Focused Ion Beam ◽  
Yield Loss ◽  
Process Analysis ◽  
Ion Beam ◽  
Yield Improvement ◽  
Transmission Electron ◽  
Defect Mechanism ◽  
Water Residue

Abstract This paper describes how the authors used a combination of focused ion beam (FIB) microprobing, transmission electron microscopy (TEM), and data and process analysis to determine that localized water residue was causing a 6% yield loss at die sort.

Relation of Rubisco to Maize Grain Yield Improvement: Effect of Water Restriction

Crop Science ◽  
1992 ◽  
Vol 32 (3) ◽  
pp. 718-722 ◽  
Author(s):  
E. Martínez‐Barajas ◽  
C. Villanueva‐Verduzco ◽  
J. Molina‐Galán ◽  
H. Loza‐Tavera ◽  
E. Sánchez‐de‐Jiménez
Keyword(s):  
Grain Yield ◽  
Water Restriction ◽  
Yield Improvement ◽  
Maize Grain Yield ◽  
Effect Of Water ◽  
Improvement Effect ◽  
Maize Grain
Sign in / Sign up

Export Citation Format

Share Document