Integrating spin-torque-transfer magnetic memory in a 65 nm low power CMOS technology

2013 ◽  
Author(s):  
Douglas Coolbaugh ◽  
Rajiv Ranjan ◽  
Ebi Abedifard ◽  
Michelle Pautler ◽  
Michael Liehr
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Magnetic Memory ◽  
Spin Torque ◽  
Spin Torque Transfer ◽  
Low Power Cmos

Ultrathin DPN STI SiON liner for 40nm low-power CMOS technology

2010 ◽  
Vol 54 (5) ◽  
pp. 564-567 ◽  
Author(s):  
Chan-Yuan Hu ◽  
Jone F. Chen ◽  
Shih-Chih Chen ◽  
Shoou-Jinn Chang ◽  
Kay-Ming Lee ◽  
...  
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Low Power Cmos

Identification of amorphous silicon residues in a low-power CMOS technology

1999 ◽  
Author(s):  
Alexandre Acovic ◽  
Philippe A. Buffat ◽  
Paul Brander ◽  
Peter J. Jacob ◽  
Oliver Jeandupeux ◽  
...  
Keyword(s):  
Low Power ◽  
Amorphous Silicon ◽  
Cmos Technology ◽  
Low Power Cmos

Ultra low power CMOS circuits working in subthreshold regime for high temperature and radiation environments

2011 ◽  
Vol 2011 (HITEN) ◽  
pp. 000243-000250 ◽  
Author(s):  
E. Boufouss ◽  
L. A. Francis ◽  
P. Gérard ◽  
M. Assaad ◽  
D. Flandre
Keyword(s):  
High Temperature ◽  
Low Power ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Cmos Circuits ◽  
Detection Level ◽  
Ultra Low Power ◽  
Temperature Detection ◽  
Low Power Cmos ◽  
Soi Cmos

We present three ultra-low-power CMOS circuits: a temperature sensor, a voltage reference and a comparator developed for an ultra-low-power microsystem (ULP-MST) aiming at temperature sensing in harsh environments. The microsystem has 3 main functions: detecting a user-defined temperature threshold T0, generating a wake-up signal that turns on a data-acquisition microprocessor (located in a safe area) above T0, and measuring temperatures above T0. To achieve ultra-low-power operation, the three CMOS circuits are implemented in Silicon-on-Insulator (SOI) CMOS technology and are optimized to work in the subthreshold regime of the transistors. Since our application is mainly for harsh environment (i.e. high temperature and radiation), the chip has been designed using a suitable 1-μm SOI-CMOS technology. Simulations have been performed over the different process corners to verify functionality after fabrication. The typical power dissipation at high temperature (up to 240°C) is less than 100 μW at 5 V supply voltage. Measurements have validated correct operation in the temperature range from −40°C to 300°C before radiation and to 125°C after radiation up to now which will be extended further with a new set-up. Irradiation has been performed from 10 to 30 kGy. Such very high doses cause a shift down of output voltage values, which leads to a change of the temperature detection level and also increases the power dissipation by up to six times. Annealing effects help the partial recovery of the device operation at high temperature and the remote microprocessor enables calibration after radiation to readjust the temperature detection level.

Sign in / Sign up

Export Citation Format

Share Document