In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

2000 ◽  
Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Failure Mechanisms ◽  
Memory Devices ◽  
Line Defect ◽  
Yield Improvement ◽  
Electrical Test ◽  
Large Numbers ◽  
Improvement Process ◽  
Existing Data

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

Integrated circuit yield statistics

1983 ◽  
Vol 71 (4) ◽  
pp. 453-470 ◽  
Author(s):  
C.H. Stapper ◽  
F.M. Armstrong ◽  
K. Saji
Keyword(s):  
Integrated Circuit ◽  
Circuit Yield

On Murphy’s Integrated Circuit Yield Integral

1995 ◽  
Vol 117 (2) ◽  
pp. 159-164
Author(s):  
John H. Lau
Keyword(s):  
Density Distribution ◽  
Closed Form ◽  
Integrated Circuit ◽  
Defect Density ◽  
Closed Form Solution ◽  
Form Solution ◽  
Simple Equation ◽  
Multichip Module ◽  
Yield Formula ◽  
Circuit Yield

An approximated closed-form integrated circuit (IC) yield formula based on a Gaussian defect density distribution for the compounder in Murphy’s yield integral is presented. Also, a closed-form solution for the average number of faults (AD0) in an IC is obtained for a given IC yield (Y). Furthermore, based on the new IC yield formula a simple equation for determining the number of yielded chips in a wafer is given. Finally, the multichip module yield (Ym) and resultant shipped multichip module yield (Yms) based on the new IC yield formula are provided.

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