Critical area based yield prediction using in-line defect classification information [DRAMs]

2002 ◽  
Author(s):  
J. Segal ◽  
A. Sagatelian ◽  
B. Hodgkins ◽  
Ben Chu ◽  
T. Singh ◽  
...  
Keyword(s):  
Defect Classification ◽  
Yield Prediction ◽  
Critical Area ◽  
Line Defect ◽  
Classification Information

Product Yield Prediction System and Critical Area Database

2008 ◽  
Vol 21 (3) ◽  
pp. 337-341 ◽  
Author(s):  
T.S. Barnett ◽  
J.P. Bickford ◽  
A.J. Weger
Keyword(s):  
Product Yield ◽  
Yield Prediction ◽  
Prediction System ◽  
Critical Area

Effects of defect propagation/growth on in-line defect-based yield prediction

1998 ◽  
Vol 11 (4) ◽  
pp. 546-551 ◽  
Author(s):  
W. Shindo ◽  
R.K. Nurani ◽  
A.J. Strojwas
Keyword(s):  
Yield Prediction ◽  
Line Defect

scholarly journals THE L∞ VORONOI DIAGRAM OF SEGMENTS AND VLSI APPLICATIONS

2001 ◽  
Vol 11 (05) ◽  
pp. 503-528 ◽  
Author(s):  
EVANTHA PAPADOPOULOU ◽  
D. T. LEE
Keyword(s):  
Voronoi Diagram ◽  
Yield Prediction ◽  
Critical Area ◽  
Vlsi Layout ◽  
Line Segments ◽  
Straight Line ◽  
Computational Bottleneck

In this paper we address the L∞ Voronoi diagram of polygonal objects and present application in VLSI layout and manufacturing. We show that L∞ Voronoi diagram of polygonal objects consists of straight line segments and thus it is much simpler to compute than its Euclidean counterpart; the degree of the computation is significantly lower. Moreover, it has a natural interpretation. In applications where Euclidean precision is not essential the L∞ Voronoi diagram can provide a better alternative. Using the L∞ Voronoi diagram of polygons we address the problem of calculating the critical area for shorts in a VLSI layout. The critical area computation is the main computational bottleneck in VLSI yield prediction.

Comprehensive methodology for integrated circuit in-line defect classification

2000 ◽  
Author(s):  
Richard L. Guldi ◽  
Douglas E. Paradis ◽  
Nagarajan Sridhar ◽  
Jesse B. Hightower
Keyword(s):  
Integrated Circuit ◽  
Defect Classification ◽  
Line Defect

The L∞ Hausdorff Voronoi Diagram Revisited

2015 ◽  
Vol 25 (02) ◽  
pp. 123-141 ◽  
Author(s):  
Evanthia Papadopoulou ◽  
Jinhui Xu
Keyword(s):  
Data Structure ◽  
Voronoi Diagram ◽  
Semiconductor Industry ◽  
Vlsi Design ◽  
Structural Complexity ◽  
Yield Prediction ◽  
Critical Area ◽  
Plane Sweep ◽  
Sweep Algorithm ◽  
Hausdorff Voronoi Diagram

We revisit the [Formula: see text] Hausdorff Voronoi diagram of clusters of points in the plane and present a simple two-pass plane sweep algorithm to construct it. This problem is motivated by applications in the semiconductor industry, in particular, critical area analysis and yield prediction in VLSI design. We show that the structural complexity of this diagram is [Formula: see text], where [Formula: see text] is the number of given clusters and [Formula: see text] is a number of specially crossing clusters, called essential. Our algorithm runs in [Formula: see text] time and [Formula: see text] space, where [Formula: see text] reflects a slight superset of essential crossings, [Formula: see text], and [Formula: see text] is the total number of crossing clusters. For non-crossing clusters ([Formula: see text]) or clusters with only a small number of crossings ([Formula: see text]) the algorithm is optimal. The latter is the case of interest in the motivating application, where [Formula: see text]. This is achieved by augmenting the wavefront data structure of the plane sweep, and a preprocessing step, based on point dominance, which is interesting in its own right.

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