Generation of New March Tests with Low Test Power and High Fault Coverage by Test Sequence Reordering Using Genetic Algorithm

2009 ◽  
Author(s):  
Gayathri C.V. ◽  
Kayalvizhi N. ◽  
Mallikadevi M.
Keyword(s):  
Genetic Algorithm ◽  
Fault Coverage ◽  
Test Sequence ◽  
Test Power ◽  
March Tests

scholarly journals Construction and application of march tests for pattern sensitive memory faults detection

Informatics ◽  
2021 ◽  
Vol 18 (1) ◽  
pp. 25-42
Author(s):  
V. N. Yarmolik ◽  
V. A. Levantsevich ◽  
D. V. Demenkovets ◽  
I. Mrozek
Keyword(s):  
Fault Detection ◽  
Multiple Testing ◽  
High Efficiency ◽  
Fault Coverage ◽  
Memory Cells ◽  
March Test ◽  
Storage Devices ◽  
Coupon Collector ◽  
March Tests ◽  
Analytical Expressions

The urgency of the problem of testing storage devices of modern computer systems is shown. The mathematical models of their faults and the methods used for testing the most complex cases by classical march tests are investigated. Passive pattern sensitive faults (PNPSFk) are allocated, in which arbitrary k from N memory cells participate, where k << N, and N is the memory capacity in bits. For these faults, analytical expressions are given for the minimum and maximum fault coverage that is achievable within the march tests. The concept of a primitive is defined, which describes in terms of march test elements the conditions for activation and fault detection of PNPSFk of storage devices. Examples of march tests with maximum fault coverage, as well as march tests with a minimum time complexity equal to 18N are given. The efficiency of a single application of tests such as MATS ++, March C− and March PS is investigated for different number of k ≤ 9 memory cells involved in PNPSFk fault. The applicability of multiple testing with variable address sequences is substantiated, when the use of random sequences of addresses is proposed. Analytical expressions are given for the fault coverage of complex PNPSFk faults depending on the multiplicity of the test. In addition, the estimates of the mean value of the multiplicity of the MATS++, March C− and March PS tests, obtained on the basis of a mathematical model describing the problem of the coupon collector, and ensuring the detection of all k2k PNPSFk faults are given. The validity of analytical estimates is experimentally shown and the high efficiency of PNPSFk fault detection is confirmed by tests of the March PS type.

scholarly journals Adaptive random testing with total cartesian distance for black box circuit under test

2020 ◽  
Vol 20 (2) ◽  
pp. 720
Author(s):  
Arbab Alamgir ◽  
Abu Khari A’ain ◽  
Norlina Paraman ◽  
Usman Ullah Sheikh
Keyword(s):  
Computational Complexity ◽  
Test Pattern ◽  
Fault Coverage ◽  
Black Box ◽  
Test Sequence ◽  
Random Testing ◽  
Subsequent Test ◽  
Adaptive Random Testing ◽  
Candidate Set ◽  
Circuit Under Test

<p>Testing and verification of digital circuits is of vital importance in electronics industry. Moreover, key designs require preservation of their intellectual property that might restrict access to the internal structure of circuit under test. Random testing is a classical solution to black box testing as it generates test patterns without using the structural implementation of the circuit under test. However, random testing ignores the importance of previously applied test patterns while generating subsequent test patterns. An improvement to random testing is Antirandom that diversifies every subsequent test pattern in the test sequence. Whereas, computational intensive process of distance calculation restricts its scalability for large input circuit under test. Fixed sized candidate set adaptive random testing uses predetermined number of patterns for distance calculations to avoid computational complexity. A combination of max-min distance with previously executed patterns is carried out for each test pattern candidate. However, the reduction in computational complexity reduces the effectiveness of test set in terms of fault coverage. This paper uses a total cartesian distance based approach on fixed sized candidate set to enhance diversity in test sequence. The proposed approach has a two way effect on the test pattern generation as it lowers the computational intensity along with enhancement in the fault coverage. Fault simulation results on ISCAS’85 and ISCAS’89 benchmark circuits show that fault coverage of the proposed method increases up to 20.22% compared to previous method.</p>

Two-Run RAM March Testing with Address Decimation

2016 ◽  
Vol 26 (02) ◽  
pp. 1750031 ◽  
Author(s):  
Ireneusz Mrozek ◽  
Vyacheslav Yarmolik
Keyword(s):  
Selection Process ◽  
Random Access ◽  
Test Session ◽  
Analytical Investigation ◽  
Fault Coverage ◽  
Test Procedures ◽  
March Test ◽  
Sequence Selection ◽  
Time Standard ◽  
March Tests

Conventional march memory tests have high fault coverage, especially for simple faults like stack-at fault (SAF), transition fault (TF) or coupling fault (CF). The same-time standard march tests, which are based on only one run, are becoming insufficient for complex faults like pattern-sensitive faults (PSFs). To increase fault coverage, the multi-run transparent march test algorithms have been used. This solution is especially suitable for built-in self-test (BIST) implementation. The transparent BIST approach presents the incomparable advantage of preserving the content of the random access memory (RAM) after testing. We do not need to save the memory content before the test session or to restore it at the end of the session. Therefore, these techniques are widely used in critical applications (medical electronics, railway control, avionics, telecommunications, etc.) for periodic testing in the field. Unfortunately, in many cases, there is very limited time for such test sessions. Taking into account the above limitations, we focus on short, two-run march test procedures based on counter address sequences. The advantage of this paper is that it defines requirements that must be taken into account in the address sequence selection process and presents a deeply analytical investigation of the optimal address decimation parameter. From the experiments we can conclude that the fault coverage of the test sessions generated according to the described method is higher than in the case of pseudorandom address sequences. Moreover, the benefit of this solution seems to be low hardware overhead in implementation of an address generator.

scholarly journals Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March Tests

2008 ◽  
Vol 18 (3) ◽  
pp. 329-339 ◽  
Author(s):  
Svetlana Yarmolik
Keyword(s):  
Selection Process ◽  
Fault Coverage ◽  
Memory Test ◽  
Memory Testing ◽  
Test Technique ◽  
Test Execution ◽  
Sequence Selection ◽  
Pattern Sensitive Faults ◽  
March Tests ◽  
Very High

Address Sequences and Backgrounds with Different Hamming Distances for Multiple Run March TestsIt is widely known that pattern sensitive faults are the most difficult faults to detect during the RAM testing process. One of the techniques which can be used for effective detection of this kind of faults is the multi-background test technique. According to this technique, multiple-run memory test execution is done. In this case, to achieve a high fault coverage, the structure of the consecutive memory backgrounds and the address sequence are very important. This paper defines requirements which have to be taken into account in the background and address sequence selection process. A set of backgrounds which satisfied those requirements guarantee us to achieve a very high fault coverage for multi-background memory testing.

scholarly journals Generation of address sequences with a given switching activity

Informatics ◽  
2020 ◽  
Vol 17 (1) ◽  
pp. 47-62
Author(s):  
V. N. Yarmolik ◽  
N. A. Shevchenko
Keyword(s):  
Random Access ◽  
Test Sequence ◽  
Storage Device ◽  
Practical Implementation ◽  
Universal Method ◽  
Switching Activity ◽  
Storage Devices ◽  
Mathematical Expressions ◽  
Generating Matrix ◽  
March Tests

The relevance of testing modern computing systems and, first of all, their storage devices is shown. The studies are based on the use of a universal method for generating the address sequences with desired      properties for multiple March tests of random access memory devices.  The modification of economical method of Antonov and Saleev is used as mathematical model to form Sobol sequences. For this model a structural diagram of its hardware implementation is presented, where the storage device for storing direction numbers is used as the basis. The set of multitudes makes up the generating matrix. It is noted that the form of the generating matrix determines the basic properties of the generated sequences. Mathematical expressions are obtained that make it possible to estimate the limiting values of switching activity, both of the sequence itself and of its individual bits. A technique is proposed for the synthesis of generators of address sequences with a given switching activity both of its individual bits and of the sequence as a whole. Examples of the application of the proposed methods are considered. The applicability of the presented results to the synthesis of test sequence generators with a given switching activity for the purpose of testing storage devices and the formation of controlled random test sequences is substantiated. The results of the practical implementation of address sequence generators are presented and their main characteristics are evaluated.

Sign in / Sign up

Export Citation Format

Share Document