Improvements to parameter extraction techniques for FDTD simulations of handset antennas

2002 ◽  
Author(s):  
M. Celuch-Marcysiak ◽  
M. Sypniewski ◽  
W.K. Gwarek
Keyword(s):  
Parameter Extraction ◽  
Extraction Techniques ◽  
Fdtd Simulations

Comparison of Parameter Extraction Techniques for SiC Schottky Diodes

2006 ◽  
Vol 911 ◽  
Author(s):  
Ming Hung Weng ◽  
Alton B. Horsfall ◽  
Nick G. Wright ◽  
Konstantin V. Vassilevski ◽  
Irina P. Nikitina
Keyword(s):  
Schottky Barrier ◽  
Barrier Height ◽  
Ideality Factor ◽  
Interfacial Layer ◽  
Schottky Diodes ◽  
Extreme Environments ◽  
Parameter Extraction ◽  
Emission Model ◽  
Schottky Barrier Diodes ◽  
Extraction Techniques

AbstractSchottky barrier diodes fabricated on Silicon carbide have been demonstrated as gas sensors for deployment in extreme environments. It has been shown that the interfacial layer formed at the Metal – Semiconductor junction, determines both the sensitivity and the reliability of the device. Hence, accurate knowledge of the thickness and interfacial trap density of this layer is required to make predictions of the behaviour of the sensor in the environment under investigation and to predict its variation with time. Diode parameters, such as the ideality factor, barrier height and series resistance have been extracted from experimental measurements on Palladium Schottky Barrier diodes on 4H SiC, over a range of temperatures. The comparison of the parameters extracted from modified Norde function, Cheung's method and Thermonic Emission model has been performed. The variation in the barrier height obtained is quite marked between the different techniques. The reverse I-V characteristics have been used to extract thickness of the interfacial layer, by fitting to the experimental data using the TEBIL model to extract the value of Dit from ä and the ideality factor, assuming the interfacial layer is stoichiometric SiO2 . This allows a comparison between the effective interfacial layer behaviour for the different parameter extraction techniques and demonstrates that knowledge of this interfacial layer is influenced by the technique selected.

DC Characterization of Different Advanced MOSFET Architectures

2011 ◽  
Vol 324 ◽  
pp. 407-410 ◽  
Author(s):  
Jalal Jomaah ◽  
Majida Fadlallah ◽  
Gerard Ghibaudo
Keyword(s):  
Low Temperature ◽  
Parameter Extraction ◽  
Gate Length ◽  
Double Gate ◽  
Extraction Techniques ◽  
Interaction Mechanisms ◽  
Dc Characterization

A review of recent results concerning the DC characterization of FD- and Double Gate SOI MOSFET’s and FinFETs in modern CMOS technologies is given. By proper extraction techniques, distinction between the different interaction mechanisms is done. Parameter extraction conducted at room and low temperature clearly indicates that the mobility is directly impacted by shrinking the gate length in sub 100nm architectures.

Sign in / Sign up

Export Citation Format

Share Document