A broadband low-noise wide dynamic range SiGe front-end receiver IC for multi-band access points

2013 ◽  
Author(s):  
Takana Kaho ◽  
Yo Yamaguchi ◽  
Hiroyuki Shiba ◽  
Munenari Kawashima ◽  
Hideki Toshinaga ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Low Noise ◽  
Wide Dynamic Range ◽  
Access Points ◽  
Front End ◽  
Multi Band

scholarly journals A 77-dB Dynamic-Range Analog Front-End for Fine-Dust Detection Systems with Dual-Mode Ultra-Low Noise TIA

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6360
Author(s):  
Reza E. Rad ◽  
Arash Hejazi ◽  
Seyed-Ali H. Asl ◽  
Khuram Shehzad ◽  
Deeksha Verma ◽  
...  
Keyword(s):  
Dynamic Range ◽  
High Sensitivity ◽  
Low Noise ◽  
Wide Dynamic Range ◽  
Maximum Gain ◽  
Detection Systems ◽  
Front End ◽  
Analog Front End ◽  
Dust Detection ◽  
Ultra Low Noise

This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset Cancellation (DCOC) circuit, a Single-to-Differential Amplifier (SDA), and two Programmable Gain Amplifiers (PGAs). Gain adjustment is implemented by a coarse-gain-step using selective loads with four different gain values and fine-gain steps by 42 dB dynamic range during 16 fine steps. The settling time of the TIA is compensated using a capacitive compensation which is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 µm standard CMOS technology. Post-layout simulations show a high gain operation with a 67 dB dynamic range, input-referred noise, less than 600 fA/√Hz in low frequencies, and less than 27 fA/√Hz at 20 kHz, a minimum detectable current signal of 4 pA, and a 2.71 mW power consumption. After measuring the full path of the analog signal conditioning path, the experimental results of the fabricated chip show a maximum gain of 142 dB for the TIA. The Single-to-Differential Amplifier delivers a differential waveform with a unity gain. The PGA1 and PGA2 show a maximum gain of 6.7 dB and 6.3 dB, respectively. The full-path analog front-end shows a wide dynamic range of up to 77 dB in the measurement results.

A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

2018 ◽  
Vol 27 (07) ◽  
pp. 1850104 ◽  
Author(s):  
Yuwadee Sundarasaradula ◽  
Apinunt Thanachayanont
Keyword(s):  
Low Power ◽  
Biomedical Applications ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Low Noise ◽  
Power Supply Voltage ◽  
Wide Dynamic Range ◽  
Dc Offset ◽  
Limiting Amplifier ◽  
Logarithmic Amplifier

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.

A low-noise wide-dynamic-range event-driven detector using SOI pixel technology for high-energy particle imaging

2015 ◽  
Author(s):  
Sumeet Shrestha ◽  
Hiroki Kamehama ◽  
Shoji Kawahito ◽  
Keita Yasutomi ◽  
Keiichiro Kagawa ◽  
...  
Keyword(s):  
Dynamic Range ◽  
High Energy ◽  
Low Noise ◽  
High Energy Particle ◽  
Energy Particle ◽  
Wide Dynamic Range ◽  
Event Driven ◽  
Particle Imaging

scholarly journals Monolithic CMOS sensor platform featuring an array of 9’216 carbon-nanotube-sensor elements and low-noise, wide-bandwidth and wide-dynamic-range readout circuitry

2019 ◽  
Vol 279 ◽  
pp. 255-266 ◽  
Author(s):  
Alexandra Dudina ◽  
Florent Seichepine ◽  
Yihui Chen ◽  
Alexander Stettler ◽  
Andreas Hierlemann ◽  
...  
Keyword(s):  
Carbon Nanotube ◽  
Dynamic Range ◽  
Low Noise ◽  
Wide Dynamic Range ◽  
Wide Bandwidth ◽  
Sensor Platform ◽  
Cmos Sensor

scholarly journals 14.85 µW Analog Front-End for Photoplethysmography Acquisition with 142-dBΩ Gain and 64.2-pArms Noise

Sensors ◽  
2019 ◽  
Vol 19 (3) ◽  
pp. 512
Author(s):  
Binghui Lin ◽  
Mohamed Atef ◽  
Guoxing Wang
Keyword(s):  
Dynamic Range ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Control Block ◽  
Silicon Area ◽  
Front End ◽  
Analog Front End

A low-power, high-gain, and low-noise analog front-end (AFE) for wearable photoplethysmography (PPG) acquisition systems is designed and fabricated in a 0.35 μm CMOS process. A high transimpedance gain of 142 dBΩ and a low input-referred noise of only 64.2 pArms was achieved. A Sub-Hz filter was integrated using a pseudo resistor, resulting in a small silicon area. To mitigate the saturation problem caused by background light (BGL), a BGL cancellation loop and a new simple automatic gain control block are used to enhance the dynamic range and improve the linearity of the AFE. The measurement results show that a DC photocurrent component up-to-10 μA can be rejected and the PPG output swing can reach 1.42 Vpp at THD < 1%. The chip consumes a total power of 14.85 μW using a single 3.3-V power supply. In this work, the small area and efficiently integrated blocks were used to implement the PPG AFE and the silicon area is minimized to 0.8 mm × 0.8 mm.

Design of a Front-End for Satellite Receiver

2016 ◽  
Vol 6 (5) ◽  
pp. 2282 ◽  
Author(s):  
Tran Van Hoi ◽  
Ngo Thi Lanh ◽  
Nguyen Xuan Truong ◽  
Nguyen Huu Duc ◽  
Bach Gia Duong
Keyword(s):  
Dynamic Range ◽  
Noise Figure ◽  
High Sensitivity ◽  
Wide Band ◽  
Local Oscillator ◽  
Low Noise ◽  
Voltage Controlled Oscillator ◽  
Front End ◽  
L Band ◽  
Satellite Receiver

<p>This paper focuses on the design and implementation of a front-end for a Vinasat satellite receiver with auto-searching mechanism and auto-tracking satellite. The front-end consists of a C-band low-noise block down-converter and a L-band receiver. The receiver is designed to meet the requirements about wide-band, high sensitivity, large dynamic range, low noise figure. To reduce noise figure and increase bandwidth, the C-band low-noise amplifier is designed using T-type of matching network with negative feedback and the L-band LNA is designed using cascoded techniques. The local oscillator uses a voltage controlled oscillator combine phase locked loop to reduce the phase noise and select channels. The front-end has successfully been designed and fabricated with parameters: Input frequency is C-band; sensitivity is greater than -130 dBm for C-band receiver and is greater than -110dBm for L-band receiver; output signals are AM/FM demodulation, I/Q demodulation, baseband signals.</p>

Low-Noise and Wide-Dynamic-Range ROIC With a Self-Selected Capacitor for SWIR Focal Plane Arrays

2017 ◽  
Vol 17 (1) ◽  
pp. 179-184 ◽  
Author(s):  
Yeong Seon Kim ◽  
Doo Hyung Woo ◽  
Young Min Jo ◽  
Sang Gu Kang ◽  
Hee Chul Lee
Keyword(s):  
Focal Plane ◽  
Dynamic Range ◽  
Low Noise ◽  
Focal Plane Arrays ◽  
Wide Dynamic Range
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