Low-noise wide-dynamic-range CMOS analog front-end IC for portable biomedical applications

2008 ◽  
Author(s):  
Yu-Pin Hsu ◽  
Chun-Hao Chen ◽  
Hsiao-Chin Chen ◽  
Shey-Shi Lu
Keyword(s):  
Biomedical Applications ◽  
Dynamic Range ◽  
Low Noise ◽  
Wide Dynamic Range ◽  
Front End ◽  
Analog Front End

scholarly journals A 77-dB Dynamic-Range Analog Front-End for Fine-Dust Detection Systems with Dual-Mode Ultra-Low Noise TIA

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6360
Author(s):  
Reza E. Rad ◽  
Arash Hejazi ◽  
Seyed-Ali H. Asl ◽  
Khuram Shehzad ◽  
Deeksha Verma ◽  
...  
Keyword(s):  
Dynamic Range ◽  
High Sensitivity ◽  
Low Noise ◽  
Wide Dynamic Range ◽  
Maximum Gain ◽  
Detection Systems ◽  
Front End ◽  
Analog Front End ◽  
Dust Detection ◽  
Ultra Low Noise

This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset Cancellation (DCOC) circuit, a Single-to-Differential Amplifier (SDA), and two Programmable Gain Amplifiers (PGAs). Gain adjustment is implemented by a coarse-gain-step using selective loads with four different gain values and fine-gain steps by 42 dB dynamic range during 16 fine steps. The settling time of the TIA is compensated using a capacitive compensation which is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 µm standard CMOS technology. Post-layout simulations show a high gain operation with a 67 dB dynamic range, input-referred noise, less than 600 fA/√Hz in low frequencies, and less than 27 fA/√Hz at 20 kHz, a minimum detectable current signal of 4 pA, and a 2.71 mW power consumption. After measuring the full path of the analog signal conditioning path, the experimental results of the fabricated chip show a maximum gain of 142 dB for the TIA. The Single-to-Differential Amplifier delivers a differential waveform with a unity gain. The PGA1 and PGA2 show a maximum gain of 6.7 dB and 6.3 dB, respectively. The full-path analog front-end shows a wide dynamic range of up to 77 dB in the measurement results.

A Low-Noise, Low-Power, Wide Dynamic Range Logarithmic Amplifier for Biomedical Applications

2018 ◽  
Vol 27 (07) ◽  
pp. 1850104 ◽  
Author(s):  
Yuwadee Sundarasaradula ◽  
Apinunt Thanachayanont
Keyword(s):  
Low Power ◽  
Biomedical Applications ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Low Noise ◽  
Power Supply Voltage ◽  
Wide Dynamic Range ◽  
Dc Offset ◽  
Limiting Amplifier ◽  
Logarithmic Amplifier

This paper presents the design and realization of a low-noise, low-power, wide dynamic range CMOS logarithmic amplifier for biomedical applications. The proposed amplifier is based on the true piecewise linear function by using progressive-compression parallel-summation architecture. A DC offset cancellation feedback loop is used to prevent output saturation and deteriorated input sensitivity from inherent DC offset voltages. The proposed logarithmic amplifier was designed and fabricated in a standard 0.18[Formula: see text][Formula: see text]m CMOS technology. The prototype chip includes six limiting amplifier stages and an on-chip bias generator, occupying a die area of 0.027[Formula: see text]mm2. The overall circuit consumes 9.75[Formula: see text][Formula: see text]W from a single 1.5[Formula: see text]V power supply voltage. Measured results showed that the prototype logarithmic amplifier exhibited an 80[Formula: see text]dB input dynamic range (from 10[Formula: see text][Formula: see text]V to 100[Formula: see text]mV), a bandwidth of 4[Formula: see text]Hz–10[Formula: see text]kHz, and a total input-referred noise of 5.52[Formula: see text][Formula: see text]V.

scholarly journals 14.85 µW Analog Front-End for Photoplethysmography Acquisition with 142-dBΩ Gain and 64.2-pArms Noise

Sensors ◽  
2019 ◽  
Vol 19 (3) ◽  
pp. 512
Author(s):  
Binghui Lin ◽  
Mohamed Atef ◽  
Guoxing Wang
Keyword(s):  
Dynamic Range ◽  
Automatic Gain Control ◽  
Gain Control ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Control Block ◽  
Silicon Area ◽  
Front End ◽  
Analog Front End

A low-power, high-gain, and low-noise analog front-end (AFE) for wearable photoplethysmography (PPG) acquisition systems is designed and fabricated in a 0.35 μm CMOS process. A high transimpedance gain of 142 dBΩ and a low input-referred noise of only 64.2 pArms was achieved. A Sub-Hz filter was integrated using a pseudo resistor, resulting in a small silicon area. To mitigate the saturation problem caused by background light (BGL), a BGL cancellation loop and a new simple automatic gain control block are used to enhance the dynamic range and improve the linearity of the AFE. The measurement results show that a DC photocurrent component up-to-10 μA can be rejected and the PPG output swing can reach 1.42 Vpp at THD < 1%. The chip consumes a total power of 14.85 μW using a single 3.3-V power supply. In this work, the small area and efficiently integrated blocks were used to implement the PPG AFE and the silicon area is minimized to 0.8 mm × 0.8 mm.

scholarly journals 22nm FINFET Based High Gain Wide Band Differential Amplifier

2021 ◽  
Vol 15 ◽  
pp. 55-62
Author(s):  
G Vasudeva ◽  
Uma B. V.
Keyword(s):  
Performance Metrics ◽  
Dynamic Range ◽  
High Gain ◽  
Low Noise ◽  
Vlsi Circuits ◽  
Differential Amplifier ◽  
Model Parameters ◽  
Front End ◽  
Analog Front End ◽  
High K

Differential Amplifier is a primary building block of analog and mixed signal circuit for pre-processing and signal conditioning of analog signal. FINFET devices with high-k gate oxide at 22nm technology are predominantly used for high speed and low power complex VLSI circuits. FINFET based differential amplifiers are widely used in ADC’s and signal Processing applications due to their advantages in terms of power dissipation. Analog front end of complex VLSI circuits need to offer high gain, higher stability and low noise figure. Designing of FINFET based VLSI sub-circuits requires proper design procedure that can provide designers flexibility in controlling the circuit performances. In this paper, differential amplifier is designed using model parameters of high-k FINFET in 22nm technology. The conventional procedures for designing MOSFET based differential amplifier are modified for designing FINFET based differential amplifier. Schematic capture is carried out in Cadence environment and simulations are obtained considering 22nm FINFET PDK. The performance metrics are evaluated and optimized considering multiple iterations. The designed differential amplifier has slew rate of 6V/µSec and settling time of 0.9 µSec which is a desired metric for ADCs. Power Supply Rejection Ratio (PSRR) is 83 dB and dynamic range is 1.6754 V. Open loop DC gain of DA is achieved to be 103 dB with phase margin of 630 that demonstrates the advantages of DA designed in this work suitable for analog front end

A broadband low-noise wide dynamic range SiGe front-end receiver IC for multi-band access points

2013 ◽  
Author(s):  
Takana Kaho ◽  
Yo Yamaguchi ◽  
Hiroyuki Shiba ◽  
Munenari Kawashima ◽  
Hideki Toshinaga ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Low Noise ◽  
Wide Dynamic Range ◽  
Access Points ◽  
Front End ◽  
Multi Band

A biasing based current mode analog front-end for biomedical applications

2021 ◽  
Author(s):  
Raja Krishnamoorthy ◽  
E. Kavitha ◽  
V. Beslin Geo ◽  
K.S.R. Radhika ◽  
C. Bharatiraja
Keyword(s):  
Biomedical Applications ◽  
Current Mode ◽  
Front End ◽  
Analog Front End
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