Design of High-speed, Low-power FIR Filters with Fine-grained Cost Metrics

2006 ◽  
Author(s):  
Jiajia Chen ◽  
Chip-Hong Chang ◽  
A. P. Vinod
Keyword(s):  
Low Power ◽  
High Speed ◽  
Fir Filters ◽  
Fine Grained ◽  
Cost Metrics

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

scholarly journals Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
M. F. Siddiqui ◽  
A. W. Reza ◽  
J. Kanesan ◽  
H. Ramiah
Keyword(s):  
Low Power ◽  
High Speed ◽  
Signal To Noise Ratio ◽  
Research Work ◽  
Coefficient Matrix ◽  
Silicon Area ◽  
Pipelined Architecture ◽  
Common Subexpression Elimination ◽  
Cost Metrics ◽  
Area Efficient

A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR) requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.

Design of high‐speed, low‐power, and area‐efficient FIR filters

2017 ◽  
Vol 12 (1) ◽  
pp. 1-11 ◽  
Author(s):  
Ahmed Liacha ◽  
Abdelkrim K. Oudjida ◽  
Farid Ferguene ◽  
Mohammed Bakiri ◽  
Mohamed L. Berrandjia
Keyword(s):  
Low Power ◽  
High Speed ◽  
Fir Filters ◽  
Area Efficient

HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

2019 ◽  
Vol 7 (1) ◽  
pp. 24
Author(s):  
N. SURESH ◽  
K. S. SHAJI ◽  
KISHORE REDDY M. CHAITANYA ◽  
◽  
◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Multiplier
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