Low power and high-speed implementation of fir filters for software defined radio receivers

2006 ◽  
Vol 5 (7) ◽  
pp. 1669-1675 ◽  
Author(s):  
A.P. Vinod ◽  
E.M.-K. Lai
Keyword(s):  
Low Power ◽  
Software Defined Radio ◽  
High Speed ◽  
Fir Filters ◽  
Radio Receivers

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

System-Level Mitigation of Undersampling ADC Nonlinearity for High-IF Radio Receivers

Frequenz ◽  
2012 ◽  
Vol 66 (9-10) ◽  
Author(s):  
Georg Vallant ◽  
Michael Epp ◽  
Markus Allén ◽  
Mikko Valkama ◽  
Friedrich K. Jondral
Keyword(s):  
Software Defined Radio ◽  
High Speed ◽  
Dynamic Range ◽  
System Level ◽  
General Validity ◽  
Radio Receivers ◽  
Rf Signals ◽  
Spurious Free Dynamic Range ◽  
Digital Linearization ◽  
Free Dynamic

AbstractOver the last years ongoing advances in ADC technology have enabled RF signals to be sampled at IF frequencies. Undersampling is nowadays employed in software-defined radio or radar receivers and offers the possibility to relieve requirements in the analog receiver partition. Unfortunately, when moving to higher IF concepts, this becomes demanding for the ADC itself, because of inherent spurious-free dynamic range (SFDR) roll-off that increases with input frequency. This fact often limits the receiver's IF placement to Nyquist zone (NZ) 2. In this work the emerging concept of Digital Assistance is pursued to give the receiver access to higher NZs while making no compromise on the SFDR. We will present and discuss post-correction results for two 16-bit high-speed converters from two different vendors at 120 and 125 MSPS, respectively. The proposed system-level post-correction decomposes nonlinearity into a static and a dynamic part. For both ADCs under investigation the degraded SFDR in higher NZs could be improved by up to 15 dB using purely digital linearization technologies, thus increasing the detectability of small signals in the presence of very strong signals or interferers. Near-identical results for both ADCs confirm the general validity of the system-level correction approach.

LTE-based passive multistatic radar for high-speed railway network surveillance: design and preliminary results

2019 ◽  
Vol 11 (5-6) ◽  
pp. 482-489
Author(s):  
Rodrigo Blázquez-García ◽  
Jorge Casamayón-Antón ◽  
Mateo Burgos-García
Keyword(s):  
Software Defined Radio ◽  
High Speed ◽  
Railway Network ◽  
High Speed Railway ◽  
Detection Range ◽  
Digital Beamforming ◽  
Radio Receivers ◽  
Network Surveillance ◽  
Multistatic Radar

AbstractWith the aim of performing perimeter surveillance of high-speed railway networks, this paper presents the design of a passive multistatic radar system based on the use of Long-Term Evolution (LTE) downlink signals as the illumination of opportunity. Taking into account the specifications and standard of the LTE system, the ambiguity function of measured downlink signals is analyzed in terms of range and Doppler resolution, ambiguities, and sidelobe level. The deployment of the proposed passive radar is flexible and scalable, and it is based on multichannel software defined radio receivers that obtain the reference and surveillance signals by means of digital beamforming. The signal processing and data fusion are based, respectively, on the delay-Doppler cross-correlation with the reconstructed reference signals and a two-stage tracking at sensor and central level. Finally, the performance of the proposed system is estimated in terms of its maximum detection range and simulation results of the detection of moving targets are presented, demonstrating its technical feasibility for the short-range detection of pedestrians, vehicles, and small drones.

Design of high‐speed, low‐power, and area‐efficient FIR filters

2017 ◽  
Vol 12 (1) ◽  
pp. 1-11 ◽  
Author(s):  
Ahmed Liacha ◽  
Abdelkrim K. Oudjida ◽  
Farid Ferguene ◽  
Mohammed Bakiri ◽  
Mohamed L. Berrandjia
Keyword(s):  
Low Power ◽  
High Speed ◽  
Fir Filters ◽  
Area Efficient
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