scholarly journals Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
M. F. Siddiqui ◽  
A. W. Reza ◽  
J. Kanesan ◽  
H. Ramiah
Keyword(s):  
Low Power ◽  
High Speed ◽  
Signal To Noise Ratio ◽  
Research Work ◽  
Coefficient Matrix ◽  
Silicon Area ◽  
Pipelined Architecture ◽  
Common Subexpression Elimination ◽  
Cost Metrics ◽  
Area Efficient

A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR) requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.

A Novel Delay-Based GFSK Demodulator in 65 nm CMOS for Low Power Biomedical Applications

2018 ◽  
Vol 10 (3) ◽  
pp. 21-32
Author(s):  
Meng Fu ◽  
Stan Skafidas ◽  
Iven Mareels
Keyword(s):  
Low Power ◽  
Biomedical Applications ◽  
Signal To Noise Ratio ◽  
Electronic Devices ◽  
Silicon Area ◽  
Novel Structure ◽  
Channel Bandwidth ◽  
Shift Keying ◽  
Mics Band ◽  
Demodulation Method

This article describes how, in recent years, with the development of microelectronics, implantable electronic devices have been playing a significant role in modem medicine. Examples of such electronic implant devices are, for instance, retinal prosthesis and brain implants. It brings great challenges in low power radio frequency (RF) and analog designs. This article presents a low power Gaussian frequency shift keying (GFSK) demodulator designed for Medical Implant Communications Service (MICS) band Receiver. This demodulator utilizes a novel structure that a wide IF range can be handled and presents the smallest Δf/f ratio in any published GFSK demodulators. In theory the demodulation method can be applied to any RF frequency. The demodulator draws 550uA from a 1 V power supply. A maximum data rate of 400 Kbits/s can be achieved within the 300 KHz channel bandwidth defined by MICS. A simulated signal-to-noise ratio (SNR) of 15.2dB at AWGN channel is obtained to achieve 10-3 bit error rate (BER). This demodulator is fabricated on 65-nm CMOS and occupies 0.12mm2 silicon area.

Low-Power and Area-Efficient Parallel Multiplier Design Using Two-Dimensional Bypassing

2016 ◽  
Vol 26 (02) ◽  
pp. 1750030 ◽  
Author(s):  
Pankaj Kumar ◽  
Rajender Kumar Sharma
Keyword(s):  
Signal Processing ◽  
Low Power ◽  
High Speed ◽  
Digital Signal ◽  
Cmos Technology ◽  
Two Dimensional ◽  
Efficient Design ◽  
Parallel Multiplier ◽  
Power Delay Product ◽  
Area Efficient

To develop low-power, high-speed and area-efficient design for portable electronics devices and signal processing applications is a very challenging task. Multiplier has an important role in digital signal processing. Reducing the power consumption of multiplier will bring significant power reduction and other associated advantages in the overall digital system. In this paper, a low-power and area-efficient two-dimensional bypassing multiplier is presented. In two-dimensional bypassing, row and column are bypassed and thus the switching power is saved. Simulation results are realized using UMC 90[Formula: see text]nm CMOS technology and 0.9[Formula: see text]V, with Cadence Spectre simulation tool. The proposed architecture is compared with the existing multiplier architectures, i.e., Braun’s multiplier, row bypassing multiplier, column bypassing multiplier and row and column bypassing multiplier. Performance parameters of the proposed multiplier are better than the existing multipliers in terms of area occupation, power dissipation and power-delay product. These results are obtained for randomly generated input test patterns having uniform distribution probability.

Novel 4:2 Approximate Compressor Designs for Multimedia and Neural Network Applications

2020 ◽  
pp. 2150138
Author(s):  
Pranose J. Edavoor ◽  
Sithara Raveendran ◽  
Amol D. Rahulkar
Keyword(s):  
Neural Network ◽  
Low Power ◽  
High Speed ◽  
Signal To Noise Ratio ◽  
Structural Similarity ◽  
Recognition System ◽  
Network Applications ◽  
Average Accuracy ◽  
Low Power Dissipation ◽  
Error Distance

Low power dissipation in approximate arithmetic circuits has laid the foundation for area-efficient computational units for error resilient applications like image and signal processing. This paper proposes two novel low power high speed architectures for approximate 4:2 compressor that can be employed in multipliers for partial product summation. The two designs presented ([Formula: see text] and [Formula: see text]) have Error Distance (ED) of [Formula: see text] and Error Rate (ER) of 25%. The proposed [Formula: see text] and [Formula: see text] are able to achieve reduction in power and delay by (62.50%, 47.67%) and (83.13%, 60.20%), respectively, in comparison with the exact 4:2 compressor. To verify the effectiveness of the design, the proposed architectures are used to implement [Formula: see text] Dadda multiplier. The equal number of errors in positive and negative directions in the proposed designs aid in reducing the Mean Error Distance (MED) and Mean Relative Error Distance (MRED) of the multiplier. Multiplication of images and two-level decomposition of 2D Haar wavelets are implemented using the designed Dadda multiplier. The efficiency of the image processing applications is measured in terms of Mean Structural Similarity (MSSIM) index and Peak Signal-to-Noise Ratio (PSNR) and an average of 0.98 and 35[Formula: see text]dB, respectively, is obtained, which are in the acceptable range. In addition, a Convolutional Neural Network (CNN)-based LeNet-1 Handwritten Digit Recognition System (HDRS) is implemented using the proposed compressor-based multipliers. The proposed compressor-based architectures are able to achieve an average accuracy of 96.23%.

A High-Speed, Low-Power, and Area-Efficient FGMOS-Based Full Adder

2019 ◽  
pp. 1-7
Author(s):  
Roshani Gupta ◽  
Rockey Gupta ◽  
Susheel Sharma
Keyword(s):  
Low Power ◽  
High Speed ◽  
Full Adder ◽  
Area Efficient
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