High-Speed Adaptive Turbo Decoding Algorithm and Its Implementation

Author(s):  
Duk Choi ◽  
Jin Jeong ◽  
Min Kim ◽  
Ji Jung
2013 ◽  
Vol 380-384 ◽  
pp. 3328-3331
Author(s):  
Jian Bing Han ◽  
Chen He ◽  
Ran Zhen

This paper introduces a new kind of decoder structure for FPGA implementation of high-speed memory efficient quasi-cyclic LDPC (QC-LDPC) decoder. The code structure, algorithm and hardware structure all adopt optimization design. The decoder adopts modified Turbo decoding algorithm and achieves a decoding throughput of 223 Mbps and frame size of 3,200 bits. The Xilinx Virtex-4 chip used by the decoder only takes up 71 KB memory and makes it exceeds other decoders in aspects of throughput and memory for FPGA implementation.


2013 ◽  
Vol 32 (8) ◽  
pp. 2113-2115
Author(s):  
Zheng LI ◽  
Chun-lin SONG ◽  
Yun-jie ZHAO ◽  
Zhu-jia WU

2014 ◽  
Vol 12 (2) ◽  
pp. 285-293
Author(s):  
Young-Jung Kim ◽  
Young-Min Cho ◽  
Jong-Yun Lee

Author(s):  
Jian Gu ◽  
Yi Zhang ◽  
Dacheng Yang ◽  
Zhen Liu

2010 ◽  
Vol 2010 ◽  
pp. 1-5 ◽  
Author(s):  
Rui Lin ◽  
Philippa A. Martin ◽  
Desmond P. Taylor

We propose a Decode-and-Forward (DF) scheme using distributed Turbo code (DTC) for a three-node (source, relay, and destination) wireless cooperative communication system. The relay decodes, then interleaves, and reencodes the decoded data. It then forwards the reencoded packet and its instantaneous receive SNR to the destination. The performances using both ideal and quantized SNR are studied. The destination uses a modified metric within a Turbo decoding algorithm to scale the soft information calculated for the relay code. The proposed scheme is simple to implement and performs well.


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